
PSB 7280
Semiconductor Group
47
Data Sheet 1998-07-01
4
Functional Blocks
4.1
PLL and Baud Rate Generator
Clocking Modes
The clock generator including PLL generates the internal master clock derived from an
input clock (or crystal) on pins XTAL(1:2).
Because of integrated decoupling capacitors, DC components of the input frequency on
XTAL(1:2) are filtered out. Consequently, for a crystal input (nearly a sinusoid), an
internal clock of nearly 50% duty cycle results.
The different clock modes available in the PSB 7280 are as follows:
For the clock generation unit (oscillator and PLL) a separate supply voltage pin (
V
DDA
and
V
DDAP
)
and a separate ground pin (
V
SSA
and
V
SSAP
)
are provided.
The block diagram of the clock circuitry is shown in
Figure 16
.
Figure 16
CM1 = 0
PLL is activated by firmware after reset. The internal clock circuitry
generates a frequency 4.5 times the input on XTAL(1,2). The internal
frequency required is 34.56 MHz and is obtained by providing a
frequency of 7.68 MHz on XTAL1 input.
PLL inactive. The internal frequency is directly input via XTAL(1,2).
When using a crystal, a 34.56 MHz crystal swinging at its basic
harmonic has to be connected to XTAL(1,2).
CM1 = 1
XTAL1
XTAL2
Oscillator
(Separate
Power supply)
VDDA, VSSA
/2
For CM1=0 (input 7,68 MHz)
x 18
/2
34.56 MHz
CM1
0
M
U
X
PLL/Clock generator circuit
DIV
CKOBR
CLKO
19
1
INT0
INT1
OR
PU
1 => set P U
DSP
AND
DSP
clock
/256
/ T3
T3
14
T3 interrupt status
CKOEN
CM1
CKOEN
T3EN
DIV
CM1
7,68 MHz
CKOS