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參數(shù)資料
| 型號： | PSB7280 |
| 廠商： | SIEMENS A G |
| 元件分類： | 消費家電 |
| 英文描述： | Joint Audio Decoder-Encoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 文件頁數(shù)： | 69/190頁 |
| 文件大?。?/td> | 2177K |
| 代理商： | PSB7280 |
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PSB 7280
Semiconductor Group
69
Data Sheet 1998-07-01
bytes (including the status byte) stored in the receive FIFO can be read out from the
receive byte count register. The receive frame status and receive byte count information
is valid after the occurrence of the RME interrupt status, and remains valid until the
software issues an acknowledgement via RMC.
In the case of frames at least 64 bytes long, the controlling software will repeatedly be
prompted by RPF to read out the FIFO in blocks of 32 bytes (except the final block). After
reading each data block, it is acknowledged RMC, which releases the FIFO. The
availability of the remainder block of length 0 to 31 bytes (excluding the status byte) is
reported via RME instead of RPF.
In the case of several consecutive short frames, the number of frames that can be stored
is only limited by the FIFO size. After an RME interrupt status, one frame is available in
the FIFO for reading. Through the RMC command the next frame is copied in the
accessible half and the corresponding space is freed in the upper (inaccessible) half.
Bits 0 - 4 of the RBC register represent the number of bytes stored in the RFIFO. Bits
5 - 15 indicate the total number of 32-byte blocks which were stored before the reception
of the remainder block.
If a frame cannot be stored due to a full FIFO, the RFO interrupt status is generated.
The RMD command is used to disable the reception of the rest of a frame after the
controlling software has checked that the frame is to be discarded (e.g. because of a
wrong address, or because of inability to process it).
Note: Only minimum length check (16 bits between flags) is performed on the receive
frame.
Details on the Operation of the HDLC Transmitter
The transmit FIFO size is 2
×
32-bytes. One half is connected with the transmit shift
register while the other half is accessible via the controlling software.
The interrupt status bits pertaining to the HDLC transmitter are:
XPR
Transmit Pool Ready
One data block may be entered into the transmit FIFO.
Transmit Data Underrun
Transmitted frame was terminated with an abort sequence because no data
was available in the transmit FIFO and yet no XME command has been
issued.
All Sent
When ‘1’, indicates that the last bit of a frame has been transmitted on the
line and that both parts of XFIFO are empty (in either HDLC or transparent
mode).
XDU
ALLS
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