
PSB 7280
Semiconductor Group
170
Data Sheet 1998-07-01
In this case, the WCB interrupt handshake is finished correctly, but the acknowledge
interrupt IND 32
H
may be missed by the host if it is busy at that time, because the next
VocFin may be generated by the JADE before the host is able to recognize the IND 32
H
interrupt. The IND interrupt status register then is overwritten by the VocFin interrupt. If
the host was busy during the time these two interrupts occured, it will afterwards only
detect the VocFin interrupt and miss the acknowledge of the WCB.
To handle this situation, the host should have an internal status register indicating an
outstanding acknowledge interrupt. In case a VocFin is detected and an acknowledge
interrupt is outstanding, the host has to check the INHB bit. As shown in
Figure 50
, the
INHB bit is reset in the WCB acknowledge procedure (see bold text). If the host detects
INHB=0, the WCB interrupt has been acknowledged, but the host has missed the IND
32
H
interrupt. If the host detects INHB=1, the WCB interrupt has not yet been serviced
and will be serviced later. For this case see also the conflict situation below.
2.
“Write JADE Control Block” conflict with “VocoderFinished”, Case 2
Another critical situation for the host may occur when a “Write JADE Control Block”
(WCB) interrupt handshake is started in parallel with the new VocoderFinished interrupt
of the new time frame.
See
Figure 51
.