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參數(shù)資料
| 型號(hào)： | PSB7280 |
| 廠商： | SIEMENS A G |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Joint Audio Decoder-Encoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 文件頁(yè)數(shù)： | 142/190頁(yè) |
| 文件大?。?/td> | 2177K |
| 代理商： | PSB7280 |
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PSB 7280
Semiconductor Group
142
Data Sheet 1998-07-01
The following steps are executed:
1. The host generates an interrupt to the JADE by writing value 33
H
into INH interrupt
status register at address 50
H
.
2. JADE writes the current status data into the mailbox, resets the INHB bit and
generates an interrupt at INT line to the host by writing a value 34
H
into IND interrupt
status register at address 58
H
.
3. The host reads the status data from the mailbox using the procedure described in
Chapter 3.3.2.2
and may reset the INDB bit. The reset of the INDB bit is not
mandatory and may be skipped. The host acknowledges the transfer by writing a
value 35
H
into INH interrupt status register at address 50
H
and by that generating an
interrupt to the JADE.
4. The JADE resets the INHB bit.
Like stated before, there is a delay of three times the frame length (default: 30 ms)
between the transfer of a new control block from the host to the JADE and the new
settings being reported in the status data (transferred from the JADE to the host) due to
the internal buffering pipeline of the JADE.
The structure of the control and status data blocks is identical. The host writes the control
block to change the settings of the JADE and reads the status block to evaluate the
current settings of the JADE.
The control/status block is organized in 8-bit words and has the following structure:
Note: Unless otherwise indicated, the host has to switch the MODE to neutral for at
least 3 frames (default: 30 ms) before it can change the control block. Only the
underlined bits may also be changed on the fly disregarding that rule. After Reset,
the JADE is automatically in the neutral mode, so changes to the control block can
be done immediately after the JADE has finished its initialization phase
(see
Chapter 6.2.3
).
(MSB)
PSEL
(LSB)
1
PF728
0
0
DM0
L0
d
EV0
DV0
CTRL
G728C
ISEL1
0
0
0
EM2
0
S
EV6
DV6
ISEL0
0
0
0
EM1
0
Re1
EV5
DV5
FLEN
UDF1
0
0
EM0
0
Re0
EV4
DV4
0
0
0
1
0
0
0
0
UDF0
0
0
DM3
0
Rd1
EV3
DV3
ET0
0
0
DM2
L2
Rd0
EV2
DV2
G722C
MODE
OPT1
OPT2
EVOL
DVOL
TM722
EM3
I
0
EV7
DV7
DM1
L1
e
EV1
DV1
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