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8.4.3
EDMA3 Peripheral Register Description(s)
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 8-3. TCI6482 EDMA3 Channel Synchronization Events (continued)
EDMA
CHANNEL
18-19
20
21-27
28
29
30
31
32
33-39
40
41-43
44
45
46-47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
BINARY
EVENT NAME
EVENT DESCRIPTION
-
-
None
RapidIO Interrupt 1
None
VCP2 receive event
VCP2 transmit event
TCP2 receive event
TCP2 transmit event
UTOPIA receive event
None
UTOPIA transmit event
None
I2C receive event
I2C transmit event
None
GPIO event 0
GPIO event 1
GPIO event 2
GPIO event 3
GPIO event 4
GPIO event 5
GPIO event 6
GPIO event 7
GPIO event 8
GPIO event 9
GPIO event 10
GPIO event 11
GPIO event 12
GPIO event 13
GPIO event 14
GPIO event 15
001 0100
-
001 1100
001 1101
001 1110
001 1111
010 0000
-
010 1000
-
010 1100
010 1101
-
011 0000
011 0001
011 0010
011 0011
011 0100
011 0101
011 0110
011 0111
011 1000
011 1001
011 1010
011 1011
011 1100
011 1101
011 1110
011 1111
INTDST1
-
VCP2REVT
VCP2XEVT
TCP2REVT
TCP2XEVT
UREVT
-
UXEVT
-
ICREVT
ICXEVT
-
GPINT0
GPINT1
GPINT2
GPINT3
GPINT4
GPINT5
GPINT6
GPINT7
GPINT8
GPINT9
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
Table 8-4. EDMA3 Channel Controller Registers
HEX ADDRESS RANGE
02A0 0000
02A0 0004
02A0 0008 - 02A0 00FC
02A0 0100
02A0 0104
02A0 0108
02A0 010C
02A0 0110
02A0 0114
02A0 0118
02A0 011C
ACRONYM
PID
CCCFG
-
DCHMAP0
DCHMAP1
DCHMAP2
DCHMAP3
DCHMAP4
DCHMAP5
DCHMAP6
DCHMAP7
REGISTER NAME
Peripheral ID Register
EDMA3CC Configuration Register
Reserved
DMA Channel 0 Mapping Register
DMA Channel 1 Mapping Register
DMA Channel 2 Mapping Register
DMA Channel 3 Mapping Register
DMA Channel 4 Mapping Register
DMA Channel 5 Mapping Register
DMA Channel 6 Mapping Register
DMA Channel 7 Mapping Register
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