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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
include information about DSP audio, video, and communications systems for the C5000 and
C6000 DSP platforms.
SPRU894
TMS320TCI648x DSP DDR2 Memory Controller User's Guide.
This document describes
the DDR2 memory controller in the TMS320TCI648x digital-signal processors (DSPs).
SPRU727
TMS320TCI648x DSP Enhanced DMA (EDMA3) Controller User's Guide.
This document
describes the Enhanced DMA (EDMA3) Controller on the TMS320TCI648x device.
SPRUE12
TMS320TCI6482 DSP EMAC/MDIO Module Reference Guide.
This document provides a
functional description of the Ethernet Media Access Controller (EMAC) and Physical layer
(PHY)
device
Management
Data
Input/Output
TMS320TCI6482 device.
(MDIO)
module
integrated
with
the
SPRU925
TMS320TCI648x DSP External Memory Interface (EMIF) User's Guide.
This document
describes the operation of the external memory interface (EMIF) in the digital signal
processors (DSPs) of the TMS320TCI648x DSP family.
SPRU725
TMS320TCI648x
document describes the general-purpose input/output (GPIO) peripheral in the digital signal
processors (DSPs) of the TMS320TCI648x DSP family. The GPIO peripheral provides
dedicated general-purpose pins that can be configured as either inputs or outputs. When
configured as an input, you can detect the state of the input by reading the state of an
internal register. When configured as an output, you can write to an internal register to
control the state driven on the output pin.
DSP
General-Purpose
Input/Output
(GPIO)
User's
Guide.
This
SPRU874
TMS320TCI648x DSP Host Port Interface (HPI) User's Guide.
This guide describes the
host port interface (HPI) on the TMS320TCI648x digital signal processors (DSPs). The HPI
enables an external host processor (host) to directly access DSP resources (including
internal and external memory) using a 16-bit (HPI16) or 32-bit (HPI32) interface.
SPRUE11
TMS320TCI648x DSP Inter-Integrated Circuit (I2C) Module User's Guide.
This document
describes the inter-integrated circuit (I2C) module in the TMS320TCI648x Digital Signal
Processor (DSP). The I2C provides an interface between the TMS320TCI648x device and
other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification
version 2.1 and connected by way of an I2C-bus. This document assumes the reader is
familiar with the I2C-bus specification.
SPRUE69
TMS320TCI648x DSP Peripheral Component Interconnect (PCI) User's Guide.
This
document describes the peripheral component interconnect (PCI) port in TMS320TCI648x
devices. See the PCI Specification revision 2.3 for details on the PCI interface.
SPRUE13
TMS320TCI648x Serial RapidIO (SRIO) User's Guide.
This document describes the Serial
RapidIO (SRIO) on the TMS320TCI648x devices.
SPRU806
TMS320TCI648x DSP Software-Programmable Phase-Locked Loop (PLL) Controller
UG.
This document describes the operation of the software-programmable phase-locked
loop (PLL) controller in the TMS320TCI648x digital signal processors (DSPs). The PLL
controller offers flexibility and convenience by way of software-configurable multipliers and
dividers to modify the input signal internally. The resulting clock outputs are passed to the
TMS320TCI648x DSP core, peripherals, and other modules inside the TMS320TCI648x
DSP.
SPRU818
TMS320TCI648x DSP 64-Bit Timer User's Guide.
This document provides an overview of
the 64-bit timer in the TMS320TCI648x DSP. The timer can be configured as a
general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdog timer. When
configured as a dual 32-bit timers, each half can operate in conjunction (chain mode) or
independently (unchained mode) of each other.
SPRUE10
TMS320TCI648x DSP Turbo-Decoder Coprocessor 2 (TCP2) Reference Guide.
Channel
Device Overview
52
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