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H1
H2
H3
N
0x1F
N+1
0x1F
N+2
0x1F
N
N+1
N+2
12
11
9
10
5
4
3
2
1
URCLK
URDATA[7:0]
URADDR[4:0]
URCLAV
URENB
URSOC
A. The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and
URSOC signals).
8
6
7
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 8-110. Timing Requirements for UTOPIA Slave Receive (see
Figure 8-77
)
-850
A-1000
-1000
NO.
UNIT
MIN
4
1
4
1
4
1
4
1
MAX
1
2
3
4
9
10
11
12
t
su(URDV-URCH)
t
h(URCH-URDV)
t
su(URAV-URCH)
t
h(URCH-URAV)
t
su(URENBL-URCH)
t
h(URCH-URENBL)
t
su(URSH-URCH)
t
h(URCH-URSH)
Setup time, URDATA valid before URCLK high
Hold time, URADDR valid after URCLK high
Setup time, URADDR valid before URCLK high
Hold time, URADDR valid after URCLK high
Setup time, URENB low before URCLK high
Hold time, URENB low after URCLK high
Setup time, URSOC high before URCLK high
Hold time, URSOC high after URCLK high
ns
ns
ns
ns
ns
ns
ns
ns
Table 8-111. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave
Receive Cycles (see
Figure 8-77
)
-850
A-1000
-1000
MIN
3
3
9
3
NO.
PARAMETER
UNIT
MAX
12
12
18.5
5
6
7
8
t
d(URCH-URCLAV)
t
d(URCH-URCLAVL)
t
d(URCH-URCLAVHZ)
t
w(URCLAVL-URCLAVHZ)
Delay time, URCLK high to URCLAV driven active value
Delay time, URCLK high to URCLAV driven inactive low
Delay time, URCLK high to URCLAV going Hi-Z
Pulse duration (low), URCLAV low to URCLAV Hi-Z
ns
ns
ns
ns
Figure 8-77. UTOPIA Slave Receive Timing
(A)
230
C64x+ Peripheral Information and Electrical Specifications
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