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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
decoding of high bit-rate data channels found in third generation (3G) cellular standards
requires decoding of turbo-encoded data. The turbo-decoder coprocessor (TCP) in some of
the digital signal processor (DSPs) of the TMS320C6000 DSP family has been designed
to perform this operation for IS2000 and 3GPP wireless standards. This document describes
the operation and programming of the TCP.
SPRU726
TMS320TCI648x DSP Universal Test & Operations PHY Interface for ATM 2 (UTOPIA2)
User's Guide.
This document describes the universal test and operations PHY interface for
asynchronous transfer mode (ATM) 2 (UTOPIA2) in the TMS320TCI648x digital signal
processors (DSPs) of the TMS320C6000 DSP family.
SPRUE09
TMS320TCI648x DSP Viterbi-Decoder Coprocessor 2 (VCP2) Reference Guide.
Channel
decoding of voice and low bit-rate data channels found in third generation (3G) cellular
standards
requires
decoding
of
convolutional
coprocessor 2 (VCP2) provided in TMS320TCI648x devices has been designed to perform
Viterbi-Decoding for IS2000 and 3GPP wireless standards. The VCP2 coprocessor has been
designed to perform forward error correction for 2G and 3G wireless systems. The VCP2
coprocessor offers a very cost effective and synergistic solution when combined with Texas
Instruments (TI) DSPs. The VCP2 can support 1941 12.2 Kbps class A 3G voice channels
running at 333 MHz. This document describes the operation and programming of the VCP2.
encoded
data.
The
Viterbi-decoder
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