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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued)
Bit
14
Field
MCBSP1_EN
Value
Description
McBSP1 Enable (MCBSP1_EN) status bit
Shows the status of which function is enabled on the McBSP1/GPIO muxed pins.
GPIO pin functions enabled (default)
McBSP1 pin functions enabled
PCI Frequency Selection (PCI66) status bit
Shows the PCI operating frequency selected at reset.
PCI operates at 33 MHz (default)
PCI operates at 66 MHz
VLYNQ Enable (VLYNQ_EN) status bit
Shows the status of which function is enabled on the VLYNQ/McBSP1/GPIO and VLYNQ/McBSP0
multiplexed pins.
McBSP1/GPIO and McBSP0 pin functions are enabled (default)
VLYNQ pin functions are enabled
PCI I2C EEPROM Auto-Initialization (PCI_EEAI) status bit
Shows whether the PCI auto-initialization via external I2C EEPROM is enabled/disabled.
PCI auto-initialization through external I2C EEPROM is disabled; the PCI peripheral uses the
specified PCI default values (default).
PCI auto-initialization through external I2C EEPROM is enabled; the PCI peripheral is configured
through external I2C EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1).
EMAC Interface Select (MACSEL[1:0]) status bits
Shows which EMAC interface mode has been selected.
10/100 EMAC/MDIO with MII Interface (default)
10/100 EMAC/MDIO with RMII Interface
10/100/1000 EMAC/MDIO with GMII Interface
10/100/1000 EMAC/MDIO with RGMII Mode Interface
[RGMII interface requires a 1.8 V or 1.5 V I/O supply]
Reserved. Read-only, writes have no effect.
UTOPIA enable (UTOPIA_EN) status bit
Shows the status of which function is enabled on the UTOPIA/EMAC and UTOPIA/MDIO
multiplexed pins.
EMAC and MDIO pin functions are enabled (default)
UTOPIA pin functions are enabled
Device Endian mode (LENDIAN)
Shows the status of whether the system is operating in Big Endian mode or Little Endian mode
(default).
System is operating in Big Endian mode
System is operating in Little Endian mode (default)
HPI bus width control bit.
Shows the status of whether the HPI bus operates in 32-bit mode or in 16-bit mode (default).
HPI operates in 16-bit mode. (default)
HPI operates in 32-bit mode
EMIFA input clock select
Shows the status of what clock mode is enabled or disabled for EMIFA.
AECLKIN (default mode)
SYSCLK4 (CPU/x) Clock Rate. The SYSCLK4 clock rate is software selectable via the PLL1
Controller. By default, SYSCLK4 is selected as CPU/8 clock rate.
0
1
13
PCI66
0
1
12
VLYNQ_EN
0
1
11
PCI_EEAI
0
1
10:9
MACSEL[1:0]
00
01
10
11
8
7
Reserved
UTOPIA_EN
0
1
6
LENDIAN
0
1
5
HPI_WIDTH
0
1
4
AECLKINSEL
0
1
Device Configuration
72
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