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Revision History
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
This data manual revision history highlights the technical changes made to the SPRS246E device-specific
data manual to make it an SPRS246F revision.
Scope:
Applicable updates to the C64x device family, specifically relating to the TMS320TCI6482 device,
have been incorporated.
Updates include documentation for device support of Advanced Event Triggering (AET) and Trace.
TCI6482 Revision History
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 1
Features:
Added High-Performance Fixed-Point DSP (TCI6482) feature:
Extended Temperature [-40
°
C to 105
°
C]
Added new features:
Advanced Event Triggering (AET) Compatible
Trace-Enabled Device
Device Characteristics:
Table 2-1
, Characteristics of the TCI6482 Processor:
Updated Cycle Time and Core Voltage
Updated Device Part Numbers
Added new Footnote (1)
Terminal Functions:
Updated description Note for EMIFA (64-BIT) - ADDRESS pins in
Table 2-3
Device Support:
Updated
Figure 2-13
, TMS320C64x+ DSP Device Nomenclature (including the TMS320TCI6482 DSP)
Device Configuration at Device Reset:
Updated paragraph and Note
Updated Footnote (1) in
Table 3-1
, TCI6482 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN)
Peripheral Selection After Device Reset:
Updated
Table 3-4
, Peripheral States
Peripheral Configuration Register 0 Description:
Changed bit 8 to TIMER
1
CTL and bit 6 to TIMER
0
CTL in
Figure 3-4
, Peripheral Configuration Register 0
(PERCFG0) and
Table 3-7
, Peripheral Configuration Register 0 (PERCFG0) Field Descriptions
Device Status Register Description:
Updated default reset values and added Note in
Figure 3-10
, Device Status Register (DEVSTAT)
Deleted Debugging Considerations section
Added new section,
Pullup/Pulldown Resistors
Changed section title to
Bus Priorities
:
Updated paragraphs
Added
Table 4-2
, TCI6482 Default Bus Master Priorities
C64x+ Megamodule Register Description(s):
Updated L2, L1P, and L1D memory protection page attribute registers and added Footnotes in
Table 5-10
,
Megamodule L1/L2 Memory Protection Registers
Device Operating Conditions:
Updated
Section 7.1
, Absolute Maximum Ratings Over Operating Case Temperature Range
Updated
Section 7.2
, Recommended Operating Conditions
Updated
Section 7.3
, Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Case Temperature
Enhanced Direct Memory Access (EDMA3) Controller:
Changed bulleted feature to
4
Quick DMA (QDMA) channels, updated last paragraph, and added Note
EDMA3 Peripheral Register Description(s):
Added DMAQNUM[4:7] Registers to
Table 8-4
, EDMA3 Channel Controller Registers
Added Memory Protection Registers to
Table 8-4
, EDMA3 Channel Controller Registers,
Table 8-6
, EDMA3
Transfer Controller 0 Registers,
Table 8-7
, EDMA3 Transfer Controller 1 Registers,
Table 8-8
, EDMA3
Transfer Controller 2 Registers, and
Table 8-9
, EDMA3 Transfer Controller 3 Registers
Interrupt Sources and Interrupt Controller:
Updated paragraph
Changed title of
Table 8-10
to
TCI6482 System Event Mapping
, updated event Descriptions, changed
Footnote (1), and deleted Footnotes (2) and (3)
Reset Controller:
Deleted Emulator as an Initiator for Max Reset in
Table 8-12
, Reset Types
Section 2.1
Section 2.7
Section 2.8.2
Section 3.1
Section 3.3
Section 3.4.2
Section 3.5
Section 3.7
Section 4.4
Section 5.7
Section 7
Section 8.4
Section 8.4.3
Section 8.5.1
Section 8.6
Revision History
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