www.ti.com
8.6.7
Reset Controller Register
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
The reset type status (RSTYPE) register (029A 00E4) is the only register for the reset controller. This
register falls in the same memory range as the PLL1 controller registers [029A 0000 - 029A 01FF] (see
Table 8-18
).
8.6.7.1
Reset Type Status Register Description
The rest type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur
simultaneously, this register latches the highest priority reset source. The reset type status register is
shown in
Figure 8-7
and described in
Table 8-13
.
31
16
Reserved
R-0
15
4
3
2
1
0
Reserved
SRST
MRST
WRST
POR
R-0
R-0
R-0
R-0
R-0
LEGEND:
R/W = Read/Write; R = Read only; -
n
= value after reset
Figure 8-7. Reset Type Status Register (RSTYPE) [Hex Address: 029A 00E4]
Table 8-13. Reset Type Status Register (RSTYPE) Field Descriptions
Bit
31:4
3
Field
Reserved
SRST
Value
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
System reset.
System Reset was not the last reset to occur.
System Reset was the last reset to occur.
Max reset.
Max Reset was not the last reset to occur.
Max Reset was the last reset to occur.
Warm reset.
Warm Reset was not the last reset to occur.
Warm Reset was the last reset to occur.
Power-on reset.
Power-on Reset was not the last reset to occur.
Power-on Reset was the last reset to occur.
0
1
2
MRST
0
1
1
WRST
0
1
0
POR
0
1
Submit Documentation Feedback
C64x+ Peripheral Information and Electrical Specifications
129