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RXD[3:0]
(A)
RXCTL
(A)
RXC
(at DSP)
(B)
5
RXERR
RXDV
6
1st Half-byte
2nd Half-byte
RXD[7:4]
RXD[3:0]
2
3
1
4
4
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 8-86. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps
(1)
(see
Figure 8-69
)
-850
A-1000
-1000
MIN
1.0
1.0
NO.
UNIT
MAX
5
6
t
su(RXD-RXCH)
t
h(RXCH-RXD)
For RGMII, receive selected signals include: RXD[3:0] and RXCTL.
Setup time, receive selected signals valid before RXC (at DSP) high/low
Hold time, receive selected signals valid after RXC (at DSP) high/low
ns
ns
(1)
A.
Data and control information is received using both edges of the clocks. RXD[3:0] carries data bits 3-0 on the rising
edge of RXC and data bits 7-4 on the falling edge of RXC. Similarly, RXCTL carries RXDV on rising edge of RXC and
RXERR on falling edge
RXC must be externally delayed relative to the data and control pins.
B.
Figure 8-69. EMAC Receive Interface Timing [RGMII Operation]
(A)(B)
Table 8-87. Switching Characteristics Over Recommended Operating Conditions for TXC - RGMII
Operation for 10/100/1000 Mbit/s (see
Figure 8-70
)
-850
A-1000
-1000
NO.
UNIT
MIN
MAX
10 Mbps
100 Mbps
1000 Mbps
10 Mbps
100 Mbps
1000 Mbps
10 Mbps
100 Mbps
1000 Mbps
10 Mbps
100 Mbps
1000 Mbps
360
36
7.2
440
44
8.8
1
t
c(TXC)
Cycle time, TXC
ns
0.40*t
c(TXC)
0.40*t
c(TXC)
0.45*t
c(TXC)
0.40*t
c(TXC)
0.40*t
c(TXC)
0.45*t
c(TXC)
0.60*t
c(TXC)
0.60*t
c(TXC)
0.55*t
c(TXC)
0.60*t
c(TXC)
0.60*t
c(TXC)
0.55*t
c(TXC)
2
t
w(TXCH)
Pulse duration, TXC high
ns
3
t
w(TXCL)
Pulse duration, TXC low
ns
0.75
0.75
0.75
4
t
t(TXC)
Transition time, TXC
ns
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