參數(shù)資料
型號： uPSD3233
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述： 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器）
文件頁數(shù)： 101/164頁
文件大?。?/td> 1133K
代理商： UPSD3233
101/164
μ
PSD3200 FAMILY
DRAFT(Thursday 20 June 2002, 13:15).
Figure 50. Data Toggle Flowchart
The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
tempted toprogram a 1 to a bit that was not erased
(not erased is logic 0).
It issuggested (as withall Flash memories)to read
the location again after the embedded program-
ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 50 still applies. the Toggle
Flag (DQ6)bit toggles untilthe Erase cycle is com-
plete. A 1 on the Error Flag (DQ5) bit indicates a
time-out condition on the Erase cycle; a 0 indi-
cates no error. The MCU can read any location
within the sector being erased to get the Toggle
Flag (DQ6) bit and the Error Flag (DQ5) bit.
PSDsoft Express generates ANSI C code func-
tions which implement these Data Toggling algo-
rithms.
Unlock Bypass.
The Unlock Bypass instructions
allow the system to program bytes to the Flash
memories faster than using the standard Program
instruction. The Unlock Bypass mode is entered
by firstinitiating twoUnlock cycles. Thisis followed
by a third Write cycle containing the Unlock By-
pass code, 20h (as shown in Table 83).
The Flash memory then enters the Unlock Bypass
mode. A two-cycle Unlock Bypass Program in-
struction is all that is required to program in this
mode. The first cycle in this instruction contains
the Unlock Bypass Program code, A0h. The sec-
ond cycle contains the program address and data.
Additional data is programmed in the same man-
ner. These instructions dispense with the initial
two Unlock cycles required in the standard Pro-
gram instruction, resulting in faster total Flash
memory programming.
During the Unlock Bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset Flash
instructions are valid.
To exit the Unlock Bypass mode, the system must
issue the two-cycle Unlock Bypass ResetFlash in-
struction. The first cycle must contain the data
90h; thesecondcycle the data00h. Addresses are
Don’t Care for both cycles. The Flash memory
then returns to Read mode.
Erasing Flash Memory
Flash Bulk Erase.
The Flash Bulk Erase instruc-
tion uses six Write operations followed by a Read
operation of the status register, as described in
Table 83. If any byte of the Bulk Erase instruction
is wrong, the Bulk Eraseinstruction aborts and the
device is reset to the Read Flash memory status.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag (DQ5) bit, the
Toggle Flag (DQ6) bit, and the Data Polling Flag
(DQ7) bit, as detailed in the section entitled “Pro-
gramming Flash Memory”, on page 100. The Error
Flag (DQ5) bit returns a 1 if there has been an
Erase Failure (maximum number of Erase cycles
have been executed).
It is not necessary to program the memory with
00h because the PSD Module automatically does
this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase.
The Sector Erase instruc-
tion uses six Write operations, as described in Ta-
ble 83. Additional Flash Sector Erase codes and
Flash memory sector addresses can be written
subsequently to erase other Flash memory sec-
tors in parallel, without further coded cycles, if the
additional bytes are transmitted in a shorter time
than thetime-out period of about 100
μ
s. The input
of a new Sector Erase code restarts the time-out
period.
The status of the internal timer can be monitored
through the levelof theEraseTime-out Flag (DQ3)
bit. If the Erase Time-out Flag (DQ3) bit is 0, the
Sector Erase instruction has been received and
the time-out period is counting. If the Erase Time-
out Flag (DQ3) bit is 1, the time-out period has ex-
pired and the embedded algorithm is busy erasing
READ
DQ5 & DQ6
START
READ DQ6
FAIL
PASS
AI01370B
DQ6
TOGGLE
NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
TOGGLE
相關(guān)PDF資料
PDF描述
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
uPSD3212C(中文) Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
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uPSD3254BV(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
UPSD3234A Flash Programmable System Devices with 8032 Microcontroller Core
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參數(shù)描述
UPSD3233A-24T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
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UPSD3233A-24T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24U1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
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