參數(shù)資料
型號： uPSD3233
廠商： 意法半導體
英文描述： Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述： 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器）
文件頁數(shù)： 75/164頁
文件大?。?/td> 1133K
代理商： UPSD3233
75/164
μ
PSD3200 FAMILY
DRAFT(Thursday 20 June 2002, 13:15).
Table 59. Description of the DDCON Register Bits
Bit
Symbol
Function
7
—
Reserved
6
EX_DAT
0 = The SRAM has 128 bytes (Default)
1 = The SRAM has 256 bytes
5
SWENB
Note: This bit is valid for DDC1 & DDC2b modes
0 = Data is automatically read from SRAM at the current location of DDCADR and sent
out via current DDC protocol. (Default)
1 = MCU is interrupted during the current data byte transmission period to load the next
byte of data to send out.
4
DDC_AX
Note: This bit is valid for DDC1 & DDC2b modes
0 = Data is automatically read from SRAM at the current location of DDCADR and sent
out via current DDC protocol. (Default)
1 = MCU is interrupted during the current data byte transmission period to load the next
byte of data to send out.
This bit only affects DDC2b Mode Operation:
0 = DDC2b I2C Address is A0/A1 (default)
1 = DDC2b I2C Address is AX. Least 3 significant address bits are ignored.
3
DDC1_Int
For DDC1 Mode Operation Only:
0 = No DDC1 interrupt
1 = DDC1 Interrupt request. Set by HW and should be cleared by SW interrupt service
routine.
Note1: This bit is set in the 9th VCLK at DDC1 enable mode. (SWENB=1)
2
DDC1EN
0 = DDC1 mode is disabled – Vsync is ignored.
The DDC unit will still respond to DDC2b requests. –provided I2C enabled.(Default)
1 = DDC1 mode is enabled.
1
SWHINT
Set by hardware when the DDC unit switches from DDC1 to DDC2b modes.
0 = No interrupt request.
1 = Switch to DDC2b mode (Interrupt pending)
Set by HW and should be cleared by SW interrupt service routine.
Note1: This bit have no connection with SWENB.
0
Mode
Current mode indication bit:
0 = Unit is in DDC1 mode
1 = Unit is in DDC2b mode
Note: When the DDC unit transitions to DDC2b mode, the DDC unit will stay in DDC2b
mode until the DDC unit is disabled, or the system is reset.
相關(guān)PDF資料
PDF描述
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
uPSD3212C(中文) Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3254A(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
uPSD3254BV(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
UPSD3234A Flash Programmable System Devices with 8032 Microcontroller Core
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3233A-24T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24T6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24U1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
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