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參數(shù)資料
| 型號： | uPSD3233 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器) |
| 中文描述： | 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器） |
| 文件頁數(shù)： | 125/164頁 |
| 文件大?。?/td> | 1133K |
| 代理商： | UPSD3233 |
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PSD3200 FAMILY
DRAFT(Thursday 20 June 2002, 13:15).
POWER MANAGEMENT
All PSD Module offers configurable power saving
options. These options maybe used individually or
in combinations, as follows:
I
The primaryand secondary Flash memory, and
SRAM blocks arebuilt with power management
technology. In addition to using special silicon
design methodology, power management
technology puts the memories into standby
mode when address/data inputs are not
changing (zero DC current). As soon as a
transition occurs on an input, the affected
memory “wakes up”, changes and latches its
outputs, then goes back to standby. The
designer doesnothave todoanything special to
achieve memory standby mode when no inputs
are changing—it happens automatically.
The PLD sections can also achieve Stand-by
mode when its inputs are not changing, as de-
scribed in the sections on the Power Manage-
ment Mode Registers (PMMR).
I
As with the Power Management mode, the
Automatic Power Down (APD) block allows the
PSD Module to reduce to stand-by current
automatically. The APD Unit can also block
MCU address/data signals from reaching the
memories andPLDs.TheAPD Unit is described
in more detail in the sections entitled “The PSD
Module has a Turbo bitin PMMR0. This bit can
be set to turn theTurbo mode off (the default is
with Turbomodeturned on). While Turbo mode
is off, the PLDs can achieve standby current
when no PLD inputs are changing (zero DC
current). Even when inputs do change,
significant power can be saved at lower
frequencies (AC current), compared to when
Turbo modeis on. When theTurbo mode is on,
there isa significant DC current component and
the AC component is higher.”, on page 126.
Built inlogic monitors the Address Strobe of the
MCU for activity. If there is no activity for a cer-
tain time period (MCU is asleep), the APD Unit
initiates Power-down mode (ifenabled). Once in
Power-down mode, all address/data signals are
blocked from reaching memory and PLDs, and
the memories are deselected internally. This al-
lows the memory and PLDs to remain in stand-
by mode even if the address/data signals are
changing state externally (noise, other devices
on the MCU bus, etc.). Keep in mind that any
unblocked PLD input signals that are changing
states keeps the PLD outof Stand-by mode, but
not the memories.
I
PSD Chip Select Input (CSI, PD2) can be used
to disable the internal memories, placing them
in standby mode even if inputs are changing.
This feature does notblock any internal signals
or disable the PLDs. This is a good alternative
to using the APD Unit. There is a slight penalty
in memory access time when PSD Chip Select
Input (CSI, PD2) makes its initial transition from
deselected to selected.
I
The PMMRs can be written by the MCU at run-
time to manage power. The PSD Module
supports “blocking bits” in these registers that
are set to block designated signals from
reaching both PLDs. Current consumption of
the PLDs is directly related to the composite
frequency of the changes on their inputs (see
Figure 69 and Figure 70). Significant power
savings can be achieved by blocking signals
that are not used in DPLD or CPLD logic
equations.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| uPSD3234(中文) | Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器) |
| uPSD3212C(中文) | Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件) |
| uPSD3254A(中文) | Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件) |
| uPSD3254BV(中文) | Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件) |
| UPSD3234A | Flash Programmable System Devices with 8032 Microcontroller Core |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPSD3233A-24T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3233A-24T1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3233A-24T6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3233A-24T6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3233A-24U1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
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