參數(shù)資料
型號: uPSD3233
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述: 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核(嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器)
文件頁數(shù): 7/164頁
文件大?。?/td> 1133K
代理商: UPSD3233
7/164
μ
PSD3200 FAMILY
DRAFT(Thursday 20 June 2002, 13:15).
SUMMARY DESCRIPTION
I
Dual bank Flash memories
– Concurrent operation, read from memory one
while erasing and writing the other. In-Appli-
cation Programming(IAP) forremote updates
– Large 128 KByte or 256 KByte main Flash
memory for application code, operating sys-
tems, or bit maps for graphic user interfaces
– Large 32 KByte secondary Flash memory di-
vided in smallsectors. Eliminate external EE-
PROM with software EEPROM emulation
– Secondary Flash memory is large enough for
sophisticated communication protocol (USB)
during IAP while continuing critical system
tasks
I
Large SRAM with battery back-up option
– 8 KByte SRAM for RTOS, high-level languag-
es, communication buffers, and stacks
I
Programmable DecodePLDfor flexibleaddress
mapping of all memories
– Place individual Flash and SRAM sectors on
any address boundary
– Built-in page register breaks restrictive 8032
limit of 64 KByte address space
– Special register swaps Flash memory seg-
ments between 8032 “program” space and
“data” space for efficient In-Application Pro-
gramming
I
High-speed clock standard 8032core (12-cycle)
– 40 MHz operation at 5 V, 24 MHz at 3.3 V
– 2 UARTs with independent baud rate, three
16-bit Timer/Counters and two External Inter-
rupts
I
USB Interface (
μ
PSD3234A-40 only)
– Supports USB 1.1 Slow Mode (1.5 Mbit/s)
– Control endpoint 0 and interrupt endpoints 1
and 2
I
I
2
C interface for peripheral connections
– Capable of master or slave operation
I
4 Pulse Width Modulator (PWM) channels
– Four 8-bit PWM units
I
Standalone Display Data Channel (DDC)
– For use in monitor, projector, and TV applica-
tions
– Compliant with VESA standards DDC1 and
DDC2B
– Eliminate external DDC PROM
I
Six I/O ports with up to 50 I/O pins
– Multifunction I/O: GPIO, DDC, I
2
C, PWM,
PLD I/O, supervisor, and JTAG
– Eliminates need for external latches and logic
I
3000 gate PLD with 16 macrocells
– Create glue logic, state machines, delays,
etc.
– Eliminate external PALs, PLDs, and 74HCxx
– Simple PSDsoft Express software ...Free
I
Supervisor functions
– Generates reset upon low voltage or watch-
dog time-out. Eliminate external supervisor
device
– Reset In pin
I
In-System Programming (ISP) via JTAG
– Program entire chip in 10 - 25 seconds with
no involvement of 8032
– Allows efficient manufacturing, easy product
testing, and Just-In-Time inventory
– Eliminate sockets and pre-programmed parts
– Program with FlashLINK
TM
cable and any PC
I
Content Security
– Programmable Security Bit blocks access of
device programmers and readers
I
Zero-Power Technology
– Memories
and PLD automatically reach
standby current between input changes
I
Packages
– 52-pin TQFP
– 80-pin TQFP:allows access to 8032address/
data/control signals for connecting to external
peripherals
相關(guān)PDF資料
PDF描述
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
uPSD3212C(中文) Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3254A(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
uPSD3254BV(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
UPSD3234A Flash Programmable System Devices with 8032 Microcontroller Core
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