參數(shù)資料
型號: uPSD3233
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述: 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核(嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器)
文件頁數(shù): 148/164頁
文件大?。?/td> 1133K
代理商: UPSD3233
μ
PSD3200 FAMILY
148/164
DRAFT(Thursday 20 June 2002, 13:15).
Table 120. CPLD Combinatorial Timing (5V devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t
PD
forMCU address and control signals refers todelay from pins on Port 0, Port2, RD WR, PSENand ALE to CPLD combinatorial
output (80-pin package only)
Table 121. CPLD Combinatorial Timing (3V devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t
PD
forMCU address and control signals refers todelay from pins on Port 0, Port2, RD WR, PSENand ALE to CPLD combinatorial
output (80-pin package only)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate
1
Unit
t
PD2
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
20
+ 2
+ 10
– 2
ns
t
EA
CPLD Input to CPLD Output
Enable
21
+ 10
– 2
ns
t
ER
CPLD Input to CPLD Output
Disable
21
+ 10
– 2
ns
t
ARP
CPLD Register Clear or Preset
Delay
21
+ 10
– 2
ns
t
ARPW
CPLD Register Clear or Preset
Pulse Width
10
+ 10
ns
t
ARD
CPLD Array Delay
Any
macrocell
11
+ 2
ns
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate
1
Unit
t
PD2
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
40
+ 4
+ 20
– 6
ns
t
EA
CPLD Input to CPLD Output
Enable
43
+ 20
– 6
ns
t
ER
CPLD Input to CPLD Output
Disable
43
+ 20
– 6
ns
t
ARP
CPLD Register Clear or
Preset Delay
40
+ 20
– 6
ns
t
ARPW
CPLD Register Clear or
Preset Pulse Width
25
+ 20
ns
t
ARD
CPLD Array Delay
Any
macrocell
25
+ 4
ns
相關(guān)PDF資料
PDF描述
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
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