參數(shù)資料
型號: uPSD3233
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述: 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核(嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器)
文件頁數(shù): 74/164頁
文件大?。?/td> 1133K
代理商: UPSD3233
μ
PSD3200 FAMILY
74/164
DRAFT(Thursday 20 June 2002, 13:15).
Special Function Register for the DDC
Interface
There are eight SFR in the DDC interface:
RAMBUF, DDCCON, DDCADR, DDCDAT are
DDC registers.
S1CON, S1STA, S1DAT, S1ADR are I
2
C Inter-
face registers, same as the ones described in the
standalone I
2
C bus.
Table 58. DDC SFR Memory Map
DDCDAT Register.
DDC1
transmission (DDCDAT: 0D5H)
I
8bit read and write register.
DATA
register
for
I
Indicates DATA BYTE to be transmitted in
DDC1 protocol.
DDCADR Register.
Address pointer for DDC in-
terface (DDCADR: 0D6H)
I
8bit read and write register.
I
Address pointer with the capability of the post
increment. After each access to RAMBUF
register (either by software or by hardware
DDC1 interface), the content of this registerwill
be increased by one. It’s available both in
DDC1, DDC2 (DDC2B, DDC2B+, and
DDC2AB) and system operation.
SFR
Addr
Reg
Name
Bit Register Name
ValueComments
7
6
5
4
3
2
1
0
D4
RAMBUF
XX
DDC Ram
Buffer
D5
DDCDAT
00
DDC Data
xmit register
D6
DDCADR
00
Addr pointer
register
D7 DDCCON
EX_DAT SWENB DDC_AX DDCINT DDC1EN SWHINT
M0
00
DDC Control
Register
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3233A-24T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
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UPSD3233A-24U1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core