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參數(shù)資料
| 型號： | uPSD3233 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器) |
| 中文描述： | 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器） |
| 文件頁數(shù)： | 119/164頁 |
| 文件大小： | 1133K |
| 代理商： | UPSD3233 |
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PSD3200 FAMILY
DRAFT(Thursday 20 June 2002, 13:15).
Direction Register.
The Direction Register, in
conjunction with the output enable (except for Port
D), controls the direction of data flow in the I/O
Ports. Any bit set to 1 in the Direction Register
causes the corresponding pin to be an output, and
any bitset to0 causes itto be aninput. The default
mode for all port pins is input.
Table 94. Port Pin Direction Control, Output
Enable P.T. Not Defined
Table 95. Port Pin Direction Control, Output
Enable P.T. Defined
Table 96. Port Direction Assignment Example
Figure 62 and Figure 63 show the Port Architec-
ture diagrams for Ports A/B and C, respectively.
The direction of data flow for Ports A,B, and C are
controlled not only by the direction register, but
also by the output enable product term from the
PLD AND Array. If the output enable product term
is not active, the Direction Register has sole con-
trol of a given pin’s direction.
An example of a configuration for a Port with the
three leastsignificant bits set tooutput and the re-
mainder set to input is shown in Table 96. Since
Port D onlycontains two pins (shownin Figure 65),
the Direction Register for Port D has only two bits
active.
Drive Select Register.
The DriveSelect Register
configures the pin driver as Open Drain or CMOS
for some port pins, and controls the slew rate for
the other port pins. An external pull-up resistor
should be usedfor pins configuredas Open Drain.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
1. The default pin drive is CMOS.
Note that the slew rate is a measurement of the
rise and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to 1. The default rate is slow slew.
Table 97 shows the Drive Register for Ports A, B,
C, and D. It summarizes which pins can be config-
ured as Open Drain outputs and which pins the
slew rate can be set for.
Port Data Registers
The Port Data Registers, shown in Table 98, are
used by the MCU to writedata to or read data from
the ports. Table 98 shows the register name, the
ports having each register type, and MCU access
for each register type. The registers are described
below.
Table 97. Drive Register Pin Assignment
Note: 1. NA = Not Applicable.
Direction Register Bit
Port Pin Mode
0
Input
1
Output
Direction
Register Bit
Output Enable
P.T.
Port Pin Mode
0
0
Input
0
1
Output
1
0
Output
1
1
Output
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port C
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port D
NA
1
NA
1
NA
1
NA
1
NA
1
Slew
Rate
Slew
Rate
NA
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPSD3233A-24T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3233A-24T1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3233A-24T6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3233A-24T6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3233A-24U1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
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