參數(shù)資料
型號： uPSD3233
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述： 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器）
文件頁數(shù)： 132/164頁
文件大?。?/td> 1133K
代理商： UPSD3233
μ
PSD3200 FAMILY
132/164
DRAFT(Thursday 20 June 2002, 13:15).
on page 96. TSTAT is High when the PSD Module
device is in Read mode (primary and secondary
Flash memory contents can be read). TSTAT is
Low when Flash memory Program or Erase cycles
are in progress, and also when data is being writ-
ten to the secondary Flash memory.
TSTAT and TERR can be configured as open-
drain type signals during an “ISC_ENABLE” com-
mand.
Security and Flash memory Protection
When the security bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port,only a Full
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the part to a
non-secured blank state. The Security Bit can be
set in PSDsoft Express Configuration.
All primary and secondary Flash memory sectors
can individually be sector protected against era-
sures. The sector protect bits can be set in PSD-
soft Express Configuration.
INITIAL DELIVERY STATE
When delivered from ST, the
μ
PSD3200 Family
device has all bits in the memory and PLDs set to
1. The code, configuration, and PLD logic are
loaded using the programming procedure. Infor-
mation for programming the device is available di-
rectly from ST. Please contact your local sales
representative.
Table 105. JTAG Enable Register
Note: 1. The state of Reset (Reset) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Configu-
ration bit (via PSDsoft Express). However, Reset (Reset) prevents or interrupts JTAG operations if the JTAG enable register is used
to enable the JTAG signals.
Bit 0
JTAG_Enable
0 = off JTAGport is disabled.
1 = on JTAGport is enabled.
Bit 1
X
0
Not used, and should be set to zero.
Bit 2
X
0
Not used, and should be set to zero.
Bit 3
X
0
Not used, and should be set to zero.
Bit 4
X
0
Not used, and should be set to zero.
Bit 5
X
0
Not used, and should be set to zero.
Bit 6
X
0
Not used, and should be set to zero.
Bit 7
X
0
Not used, and should be set to zero.
相關(guān)PDF資料
PDF描述
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
uPSD3212C(中文) Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3254A(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
uPSD3254BV(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
UPSD3234A Flash Programmable System Devices with 8032 Microcontroller Core
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3233A-24T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24T6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24U1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*