參數(shù)資料
型號: uPSD3233
廠商: 意法半導體
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述: 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核(嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器)
文件頁數(shù): 126/164頁
文件大小: 1133K
代理商: UPSD3233
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PSD3200 FAMILY
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DRAFT(Thursday 20 June 2002, 13:15).
Figure 66. APD Unit
The PSD Module has a Turbo bit in PMMR0. This
bit can be set to turn the Turbo mode off (the de-
fault is with Turbo mode turned on). While Turbo
mode is off,the PLDscan achieve standby current
when no PLD inputs are changing (zero DC cur-
rent). Even when inputs do change, significant
power can be saved at lower frequencies (AC cur-
rent), compared to when Turbo mode is on. When
the Turbomode is on,there is a significantDCcur-
rent component and the AC component is higher.
Automatic Power-down (APD) Unit and Power-
down Mode.
The APD Unit, shown in Figure 66,
puts the PSD Module into Power-down mode by
monitoring the activity of Address Strobe (ALE). If
the APD Unit is enabled, assoon as activity onAd-
dress Strobe (ALE) stops, a four bit counter starts
counting. If Address Strobe (ALE/AS, PD0) re-
mains inactive for fifteen clock periods of CLKIN
(PD1), Power-down (PDN) goes High, and the
PSD Module enters Power-down mode, as dis-
cussed next.
Power-down Mode.
By default, if you enable the
APD Unit, Power-down mode is automatically en-
abled. Thedevice enters Power-down mode if Ad-
dress Strobe (ALE) remains inactive for fifteen
periods of CLKIN (PD1).
The following should be kept in mind when the
PSD Module is in Power-down mode:
I
IfAddress Strobe(ALE)starts pulsing again,the
PSD Module returns to normalOperating mode.
The PSD Module also returns to normal
Operating mode if either PSD Chip Select Input
(CSI, PD2)isLowor the Reset(RESET)input is
High.
I
The MCU address/data bus is blocked from all
memory and PLDs.
I
Various signals can be blocked (prior to Power-
down mode) from entering the PLDs by setting
the appropriate bits in the PMMR registers. The
blocked signals include MCU control signals
and the common CLKIN (PD1). Note that
blocking CLKIN (PD1) from the PLDs does not
block CLKIN (PD1) from the APD Unit.
I
All memories enter Standby mode and are
drawing standbycurrent.However, thePLD and
I/O ports blocks do not go into Standby Mode
because you don’t want to have to wait for the
logic and I/O to “wake-up” before their outputs
can change. See Table 99 for Power-down
mode effects on PSD Module ports.
I
Typical standby current is of the order of
microamperes. These standby current values
assume thatthere arenotransitions onanyPLD
input.
Other Power Saving Options.
The PSD Module
offers other reduced power saving optionsthat are
independent of the Power-down mode. Except for
the SRAM Stand-by and PSD Chip Select Input
(CSI, PD2) features, they are enabled by setting
bits in PMMR0 and PMMR2.
Table 99. Power-down Mode’s Effect on Ports
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN)
SELECT
DISABLE BUS
INTERFACE
CSIOP SELECT
FLASH SELECT
SRAM SELECT
PD
CLR
PD
DISABLE
FLASH/SRAM
PLD
AI06608
Port Function
Pin Level
MCU I/O
No Change
PLD Out
No Change
Address Out
Undefined
Peripheral I/O
Tri-State
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