參數(shù)資料
型號： uPSD3233
廠商： 意法半導體
英文描述： Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述： 閃存可編程系統(tǒng)器件與8032微控制器內核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器）
文件頁數(shù)： 78/164頁
文件大小： 1133K
代理商： UPSD3233
μ
PSD3200 FAMILY
78/164
DRAFT(Thursday 20 June 2002, 13:15).
DDC1 Protocol
DDC1 is primitive and a point to point interface.
The monitoris always putat “Transmit only” mode.
In the initialization phase, 9 clock cycles on VCLK
pin will be given for the internal synchronization.
During this period,the SDA pin will be kept at high
impedance state.
If DDC1 hardwaremode is used, the following pro-
cedure is recommended to proceed DDC1 opera-
tion.
1. Reset DDC1enable (bydefault, DDC1 enableis
cleared as LOW after power on reset).
2. Set SWENB as high (the default value is zero.)
3. Depending on the data size of EDID data, set
EX_DAT as LOW (128 bytes) or HIGH (256
bytes).
4. By using bulky moving commands (DDCADR,
RAMBUF involved) to move the entire EDID
data to RAM buffer.
5. Reset SWENB to LOW.
6. Reset DDCADR to 00h.
7. Set DDC1 enable as HIGH.
In case SWENB is set as high, interrupt service
routine is finished within 133 machine cycle in 40
MHz System clock.
The maximum Vsync (VCLK) frequency is 25Khz
(40
μ
s). And the 9th clock of Vsync (VCLK) is inter-
rupt period.
So the machine cycle be needed is calculated as
below. For example,
When 40 MHz system clock, 40
μ
s= 133 x (25 ns
x 12); 133 machine cycle.
12 MHz system clock, 40
μ
s = 40 x (83.3 ns x12);
40 machine cycle.
8 MHz system clock, 40
μ
s = 26 x (125 ns x 12);
26 machine cycle.
Note: If EX_DAT equals to LOW, it is meant the lower partis occu-
pied by DDC1 operation and the upper part is still free to the
system. Nevertheless, the effect of the post increment just
applies to the part related toDDC1 operation. In other words,
the system program is still able to address the locations from
128 to 255 in the RAM buffer through MOVX command but
without the facility of the post increment. For example, the
case of accessing 200 of the RAM Buffer:
MOV R0, #200
MOVX A, @R0
Figure 39. Transmission Protocol in the DDC1 Interface
AI06652
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
B
tSU(DDC1)
tDOV
Hi-Z
SC
VCLK
DDC1INT
DDC1EN
SD
tH(VCLK)
tL(VCLK)
Max=40us
B
B
B
B
B
B
B
B
HiZ
相關PDF資料
PDF描述
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
uPSD3212C(中文) Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3254A(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內核的FLASH可編程系統(tǒng)器件)
uPSD3254BV(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內核的FLASH可編程系統(tǒng)器件)
UPSD3234A Flash Programmable System Devices with 8032 Microcontroller Core
相關代理商/技術參數(shù)
參數(shù)描述
UPSD3233A-24T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24T6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24U1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
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