參數(shù)資料
型號: uPSD3233
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述: 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核(嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器)
文件頁數(shù): 32/164頁
文件大?。?/td> 1133K
代理商: UPSD3233
μ
PSD3200 FAMILY
32/164
DRAFT(Thursday 20 June 2002, 13:15).
Table 17. PSD Module Register Address Offset
CSIO
PAddr
Offset
Register Name
Bit Register Name
Reset
Value
Comments
7
6
5
4
3
2
1
0
00
Data In (Port A)
Reads Port pins as input
02
Control (Port A)
Configure pin between I/O or Address Out mode. Bit = 0 selects
I/O
00
04
Data Out (Port
A)
Latched data for output to Port pins, I/O output mode
00
06
Direction (Port
A)
Configures Port pin as input or output. Bit = 0 selects input
00
08
Drive (Port A)
Configures Port pin between CMOS, Open Drain or Slew rate. Bit
= 0 selects CMOS
00
0A
Input Macrocell
(Port A)
Reads latched value on Input Macrocells
0C
Enable Out(Port
A)
Reads the status of the output enable control to the Port pin
driver. Bit = 0 indicates pin is in input mode.
01
Data In (Port B)
03
Control (Port B)
00
05
Data Out (Port
B)
00
07
Direction (Port
B)
00
09
Drive (Port B)
00
0B
Input Macrocell
(Port B)
0D
Enable Out(Port
B)
10
Data In (Port C)
12
Data Out (Port
C)
00
14
Direction (Port
C)
00
16
Drive (Port C)
00
18
Input Macrocell
(Port C)
1A
Enable Out(Port
C)
11
Data In (Port D)
*
*
*
*
*
*
Only Bit 1and
2 are used
13
Data Out (Port
D)
*
*
*
*
*
*
00
Only Bit 1and
2 are used
15
Direction (Port
D)
*
*
*
*
*
*
00
Only Bit 1and
2 are used
17
Drive (Port D)
*
*
*
*
*
*
00
Only Bit 1and
2 are used
相關(guān)PDF資料
PDF描述
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
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uPSD3254A(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
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