參數(shù)資料
型號： uPSD3233
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
中文描述： 閃存可編程系統(tǒng)器件與8032微控制器內(nèi)核（嵌入高速“8032微控制器核”的閃存型可編程系統(tǒng)器）
文件頁數(shù)： 68/164頁
文件大?。?/td> 1133K
代理商： UPSD3233
μ
PSD3200 FAMILY
68/164
DRAFT(Thursday 20 June 2002, 13:15).
Table 48. Serial Control Register (SxCON: S1CON, S2CON)
Table 49. Description of the SxCON Bits
Table 50. Selection of the Serial Clock Frequency SCL in Master Mode
7
6
5
4
3
2
1
0
CR2
ENII
STA
STO
ADDR
AA
CR1
CR0
Bit
Symbol
Function
7
CR2
This bit along with bits CR1and CR0 determines the serial clock frequency when SIO is
in the Master mode.
6
ENII
Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are in the high
impedance state.
5
STA
START flag. When this bit is set, theSIO H/W checks the status of the I
2
C-bus and
generates a STARTcondition if the bus free. If the bus is busy, the SIO will generate a
repeated START condition when this bit is set.
4
STO
STOP flag. With this bit set while in Master mode a STOP condition is generated.
When a STOP condition is detected on the I
2
C-bus, the I
2
C hardware clears the STO
flag.
Note: This bit have to be set before 1 cycle interrupt period of STOP.That is, if this bit is
set, STOP condition in master mode is generated after 1 cycle interrupt period.
3
ADDR
This bit is set when address byte was received. Must be cleared by software.
2
AA
Acknowledge enable signal. If this bit is set, an acknowledge (low level to SDA) is
returned during the acknowledge clock pulse on the SCL line when:
Own slave address is received
A data byte is received while the device is programmed to be a Master Receiver
A data byte is received while the device is a selected Slave Receiver. When this bit is
reset, no acknowledge is returned.
SIO release SDA line as high during the acknowledge clock pulse.
1
CR1
These two bits along with the CR2 bit determine the serial clock frequency when SIO is
in the Master mode.
0
CR0
CR2
CR1
CR0
F
OSC
Divisor
Bit Rate (kHz) at F
OSC
12 MHz
24 MHz
36 MHz
40 MHz
0
0
0
16
375
750
X
X
0
0
1
24
250
500
750
833
0
1
0
30
200
400
600
666
0
1
1
60
100
200
300
333
1
0
0
120
50
100
150
166
1
0
1
240
25
50
75
83
1
1
0
480
12.5
25
37.5
41
1
1
1
960
6.25
12.5
18.75
20
相關(guān)PDF資料
PDF描述
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
uPSD3212C(中文) Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3254A(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
uPSD3254BV(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
UPSD3234A Flash Programmable System Devices with 8032 Microcontroller Core
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3233A-24T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24T6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233A-24T6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3233A-24U1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
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