參數(shù)資料
型號: E-110
廠商: LSI Corporation
英文描述: 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core)
中文描述: 100兆- T的快速以太網(wǎng)核心(100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心)
文件頁數(shù): 108/130頁
文件大?。?/td> 770K
代理商: E-110
5-2
Specifications
5.2 MAC Core AC Timing
This section provides a list of signals that must operate properly with
respect to the MTXC, MRXC, and HCLK signals. The relationship
between the signals is depicted in Figure 5.1.
The numbers in Figure 5.1 refer to the AC timing parameters listed in
the first column of Table 5.1. The core has been verified under worst-
case process voltage and ambient temperature.
Figure 5.1
MAC Core Setup, Hold, and Delay Timing Diagram
1, 3, 5, 7, 33, 35, 37
2, 4, 6, 8, 34, 36, 38
MTXC
MRXC
Inputs
Valid
Outputs
Valid
9, 10, 11, 12, 13, 14, 39
29, 31
30, 32
Inputs
Valid
Valid
15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 40
Outputs
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