參數(shù)資料
型號: E-110
廠商: LSI Corporation
英文描述: 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core)
中文描述: 100兆- T的快速以太網(wǎng)核心(100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心)
文件頁數(shù): 112/130頁
文件大小: 770K
代理商: E-110
5-6
Specifications
5.4 MAC Control Module Core AC Timing
This section gives a list of the signals that must operate properly with
respect to the MTXC and MRXC signals. The relationship between the
signals is depicted in Figure 5.2. The numbers in Figure 5.2 refer to the
AC timing parameters listed in the first column of Table 5.3. The MAC
control module core has been verified under worst-case process, voltage,
and ambient temperature.
TPD[7:0]
Transmit Packet Data
Input
TPDN
Transmit Packet Done
Output
HIGH
TPEF
Transmit Packet End of Frame
Input
HIGH
TPRT
Transmit Packet Retry
Output
HIGH
TPSF
Transmit Packet Start Of Frame
Input
HIGH
TPUD
Transmit Packet Data Used
Output
HIGH
TPUR
Transmit Packet Data Underrun
Input
HIGH
TRST_L
Transmit Reset
Output
LOW
TSV[30:0]
Transmit Statistics Vector
Output
TSVP_L
Transmit Statistics Vector Pulse
Output
LOW
Table 5.2
MAC Core Pin Summary (Cont.)
Mnemonic
Description
Type
Active
(Sheet 3 of 3)
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