參數(shù)資料
型號(hào)： E-110
廠商： LSI Corporation
英文描述： 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core)
中文描述： 100兆- T的快速以太網(wǎng)核心（100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心）
文件頁數(shù)： 94/130頁
文件大?。?/td> 770K
代理商： E-110
3-22
Core Descriptions
5
Auto-Negotiation
Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
R/O
4
Remote Fault
1 = Remote fault condition detected
0 = No remote fault condition detected
R/O, LH
4
3
Auto-Negotiation
Ability
1 = PHY is able to perform auto-negotiation
0 = PHY is not able to perform auto-negotiation
R/O
2
Link Status
1 = Link is up
0 = Link is down
R/O, LL
5
1
Jabber Detect
1 = Jabber condition detected. Jabber is defined as a condi-
tion on an Ethernet network when a node transmits for longer
than the specified time.
0 = No jabber condition detected
R/O, LH
0
Extended
Capability
1 = Extended register capabilities
0 = Basic register capabilities
R/O
1. 100BASE-T4 allows users to run 100BASE-T over four pairs of Category 3, 4, or 5 UTP cabling.
2. R/O = Read-Only.
3. 100BASE-TX allows users to run 100BASE-T over two pairs of Category 5 UTP and Type 1 STP.
4. LH = Latching High. When a fault condition occurs (remote fault or jabber), the bit is set. The bit
remains set until the PHY status register is read via the MIIM or the PHY is reset, at which time the
bit is cleared.
5. LL = Latching Low. When the link is not valid, the PHY clears the bit. It remains cleared until the
PHY status register is read via the MIIM. The bit is set when the PHY has determined that a valid
link has been established.
Table 3.3
PHY Status Register Bit Definitions (Cont.)
Bit
Name
Description
Operation
(Sheet 2 of 2)
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