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參數(shù)資料
| 型號(hào)： | E-110 |
| 廠商： | LSI Corporation |
| 英文描述： | 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core) |
| 中文描述： | 100兆- T的快速以太網(wǎng)核心（100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心） |
| 文件頁(yè)數(shù)： | 43/130頁(yè) |
| 文件大?。?/td> | 770K |
| 代理商： | E-110 |
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MAC Core Signals
2-11
The PHY ensures that MCRS remains asserted through-
out the duration of a collision condition.
MRXC
Receive Nibble or Symbol Clock
The MRXC [RX_CLK] signal is a continuous clock that
provides a timing reference for transfer of the MRXDV
[RX_DV], MRXD[3:0] [RXD], and MRXER [RX_ER] sig-
nals from the PHY to the E-110 MAC. MRXC is an input
from the PHY.
Input
As long as the PHY is receiving a continuous signal from
the medium and can recover the MRXC clock reference
and supply MRXC, the PHY does not need to make a
switch from the recovered clock reference to a nominal
clock reference (for example, the MTXC [TX_CLK] contin-
uous clock signal from the PHY). However, if the loss of
a receive signal causes the PHY to lose the recovered
clock reference, the PHY must source MXRC from a
nominal clock reference.
If the PHY needs to make a switch from recovered clock
to nominal clock, it deasserts the MRXDV signal. During
the interval between MCRS and the assertion of MRXDV
at the beginning of a frame, the PHY may extend a cycle
of the MRXC clock by holding it in either the HIGH or
LOW condition until the PHY has successfully locked
onto the recovered clock. Successive cycles of MRXC
must meet the duty cycle requirement.
While MRXDV is asserted, the PHY recovers MRXC from
the received data. MRXC has a frequency equal to 25%
of the data rate of the received signal and is synchronous
to recovered data. The duty cycle is between 35% and
60% and is nominally 50%. For 100-Mbit/s operation,
MRXC is nominally 25 MHz
±
100 ppm, and the minimum
MRXC HIGH and LOW times are 14 ns. For 10-Mbit/s
operation, MRXC is nominally 2.5 MHz
±
100 ppm, and
the minimum MRXC HIGH and LOW times are 140 ns.
When the MCRS signal is deasserted, the PHY provides
MRXC at the PHY’s nominal clock rate (for example, the
MTXC clock signal) and with nominal duty cycle. The
minimum HIGH and LOW times are each 35% of the
nominal MRXC period except for the transition between
recovered clock frequency and nominal clock frequency,
which occurs while MRXDV is deasserted. Following the
transition from MRXDV asserted to MRXDV deasserted,
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