參數(shù)資料
型號: E-110
廠商: LSI Corporation
英文描述: 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core)
中文描述: 100兆- T的快速以太網(wǎng)核心(100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心)
文件頁數(shù): 114/130頁
文件大小: 770K
代理商: E-110
5-8
Specifications
5.5 MAC Control Module Core Pin Summary
Table 5.4 summarizes the MAC control module core signals.
21.
TPAB setup to MTXC
22.
TPAB hold time after MTXC
23.
TPDN setup to MTXC
24.
TPDN hold time after MTXC
25.
TPSF delay after MTXC
26.
TRST_L setup to MTXC
27.
TRST_L hold time after MTXC
Table 5.3
MAC Control Module AC Timing Parameters (Cont.)
Parameter
Description
Parameter
Description
(Sheet 2 of 2)
Table 5.4
MAC Control Module Pin Summary
Mnemonic
Description
Type
Active
ADDR_MATCH
Unicast Address Match
Input
HIGH
CTLP
Host Control Packet Transmit Request
Input
HIGH
FLOWCON_EN
Flow Control Enable
Input
HIGH
HST_TPSF
Host Packet Transmit Request
Input
HIGH
MRXC
Receive Nibble or Symbol Clock
Input
MTXC
Transmit Nibble or Symbol Clock
Input
PAUSE_ACTIVE
Pause in Progress
Output
HIGH
PAUSE_MIRROR[23:0]
Pause Mirror Counter Value
Output
PAUSE_RSVP_L
Comprehensive Receive Statistics Vector Pulse Output
LOW
PAUSE_TIME_IN[15:0]
Transmitted Pause Time
Input
RCV_LOAD_DLY[3:0]
Receiver Delay in Loading Transmitted Pause
Input
RCVNG_PAUSE_FRAME
Receiving Pause Frame
Output
HIGH
RPD[7:0]
Receive Packet Data
Input
(Sheet 1 of 2)
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