參數(shù)資料
型號: E-110
廠商: LSI Corporation
英文描述: 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core)
中文描述: 100兆- T的快速以太網(wǎng)核心(100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心)
文件頁數(shù): 70/130頁
文件大?。?/td> 770K
代理商: E-110
2-38
Signal Descriptions
PRSD[15:0] signals are valid after the MIIM core deas-
serts BUSY for a read operation and after the MIIM core
deasserts NVALID for a scan operation. See Section
3.2.3.2, “Read PHY Status Register,” on page 3-21 for a
definition of the PHY Status register.
RGAD[4:0]
Register Address [4:0]
The RGAD[4:0] signals contain the address of the regis-
ter within the PHY the host has selected for reading or
writing. The host must not change the RGAD[4:0] signals
while the MIIM core is asserting the BUSY signal; other-
wise, the MIIM core may read the RGAD[4:0] signals
incorrectly.
Input
RSTAT
Request MII Status
The host asserts the RSTAT signal to request that the
MIIM function initiate a status read operation from the
addressed MII PHY. RSTAT must be at least one HCLK
pulse wide and must be asserted and deasserted syn-
chronously with the rising edge of HCLK. The host must
ensure that FIAD[4:0] and RGAD[4:0] are valid before it
asserts RSTAT. The host must keep the RSTAT signal
deasserted if the SCAN signal is asserted.
Input
SCAN
Status Read Scan
When the host asserts the SCAN signal, the MIIM core
causes continuous status read operations from the
addressed MII PHY. The host must ensure that FIAD[4:0],
and RGAD[4:0] are valid before it asserts SCAN and
must not change the signals during the entire scan
operation. When the host deasserts SCAN, status read
operations stop.
Input
SCAN must be at least one HCLK pulse wide and must
be asserted and deasserted synchronously with the
rising edge of HCLK.
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