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參數(shù)資料
| 型號： | E-110 |
| 廠商： | LSI Corporation |
| 英文描述： | 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core) |
| 中文描述： | 100兆- T的快速以太網(wǎng)核心（100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心） |
| 文件頁數(shù)： | 24/130頁 |
| 文件大小： | 770K |
| 代理商： | E-110 |
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1-16
Introduction
which means that accesses to the statistics storage by the host are
automatically synchronized. However, the transmit and receive statistics
vector latch pulse must be synchronized to the host system clock
because the transmit and receive functions operate on their own clocks.
1.4.1.3 Host Processor Interface
The host system processor has the following connections to the E-110
MAC:
MII Data Interface
Random Number Generator Interface
Control Interface
Statistics Interface
MII Data Interface –
The E-110 MAC sends and receives data to the
MII-supported PHY by means of the MII Transmit Data and Receive Data
signal lines, over which the MAC passes transmit and receive nibbles.
Random Number Generator Interface –
The E-110 MAC contains a
random number generator that is used for transmit backoff in the event
of a collision. The host may optionally load an 11-bit seed value into the
random number generator. By loading different seed values into each
E-110 MAC in a multiple-MAC system, you can guarantee that the
backoff timers in each MAC are not synchronized to each other, which
avoids the problem of two or more MACs colliding repeatedly while
attempting to transmit. If you do not load a seed value in the random
number generator, there is a chance that two MACs might have the same
backoff timer value.
Control Interface –
The host control interface allows the host to directly
control the operation of the E-110 MAC. The host must provide either a
25- or 33-MHz clock (HCLK) to the core. The core uses the clock select
(CLKS) input signal from the host to determine how to divide down HCLK
to create the MIIM Data Clock (MDC) signal. The host provides a variety
of control signals to the MAC function to control the following:
Interpacket gaps (see Section 3.2.1.1, “MAC Transmit Function,” and
the signal descriptions for IPGR1[6:0], IPGR2[6:0], and IPGT[6:0] in
Chapter 2).
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| E110.000 | 功能描述:折皺器 Ferrule Crimper 26-10 AWG RoHS:否 制造商:Hirose Connector 類型: 描述/功能:Cable and Shield Crimper |
| E110.005 | 功能描述:折皺器 UNIV FERRULE CRIMPER 20-8 AWG 0.5-10 RoHS:否 制造商:Hirose Connector 類型: 描述/功能:Cable and Shield Crimper |
| E110.010 | 功能描述:折皺器 FERRULE CRIMPER 8-6AWG RoHS:否 制造商:Hirose Connector 類型: 描述/功能:Cable and Shield Crimper |
| E110.015 | 功能描述:折皺器 FERRULE CRIMPER 4-2AWG 25-35 RoHS:否 制造商:Hirose Connector 類型: 描述/功能:Cable and Shield Crimper |
| E110.020 | 功能描述:折皺器 FERRULE CRIMPER 1 AWG 50 RoHS:否 制造商:Hirose Connector 類型: 描述/功能:Cable and Shield Crimper |
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