參數(shù)資料
型號(hào): E-110
廠商: LSI Corporation
英文描述: 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core)
中文描述: 100兆- T的快速以太網(wǎng)核心(100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心)
文件頁數(shù): 75/130頁
文件大?。?/td> 770K
代理商: E-110
E-110 Core Operation
3-3
3.1.2 HCLK
The host clock is either a 33-MHz or 25-MHz clock. The CLKS signal
indicates the HCLK frequency to the MIIM core. The host clock
generates the MIIM Data Clock (MDC), which has minimum HIGH and
LOW times of 200 ns each. A 33-MHz HCLK is divided by 14 to generate
a 2.35 MHz MDC and a 25-MHz HCLK is divided by 10 to generate a
2.5 MHz clock. To meet the minimum HIGH and LOW times, the
maximum frequency of MDC is 2.5 MHz.
3.1.3 MDC
The MDC signal is the MIIM core data clock output. The MDC [MDC]
signal is sent by the core to the PHY as a timing reference for transfer
of information on the MDI and MDO signal lines. MDC is an aperiodic
signal that has no maximum HIGH or LOW times. The minimum HIGH
and LOW times are 200 ns each.
3.2 E-110 Core Operation
The following subsections describe the operation of the E-110 core.
Figure 3.1 is an overall block diagram, showing how the MAC receive and
transmit functions, MIIM core, and MAC control module core interface to
the host and the PHY.
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