參數(shù)資料
型號: E-110
廠商: LSI Corporation
英文描述: 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core)
中文描述: 100兆- T的快速以太網(wǎng)核心(100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心)
文件頁數(shù): 91/130頁
文件大小: 770K
代理商: E-110
E-110 Core Operation
3-19
3.2.3.1 Write PHY Control Register
To write the Control Register in the PHY, the host places the PHY
address on the MIIM core’s FIAD[4:0] signals and the address of the
Control Register within the PHY on the core’s RGAD[4:0] signals. The
host keeps the RSTAT signal deasserted during a write operation.
The host CTLD[15:0] signals contain the data that is sent to the PHY
Control Register. When the host asserts the LCTLD signal, the data on
the FIAD[4:0], RGAD[4:0], and CTLD[15:0] buses are loaded into the
MIIM core, and the core asserts the BUSY signal. The host must not
change any of the address or data lines while BUSY is asserted. During
the time the MIIM core asserts BUSY, it uses the MDO, MDC, and
MDOEN signals to transport data to the Control Register of the selected
PHY, using the Management Frame Format specified in the MII
specification. The MDO and MDI signals are normally connected to a
3-state bidirectional transceiver on the PHY side of the MIIM core. A
single bidirectional data line from the transceiver, MDIO, transfers control
and status data to and from the PHY. The MDOEN signal controls the
transceiver direction.
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