參數(shù)資料
型號(hào): E-110
廠商: LSI Corporation
英文描述: 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core)
中文描述: 100兆- T的快速以太網(wǎng)核心(100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心)
文件頁數(shù): 77/130頁
文件大小: 770K
代理商: E-110
E-110 Core Operation
3-5
3.2.1 MAC Core Operation
Figure 3.2 shows the E-110 MAC core transmit and receive function
blocks, along with customer-defined transmit and receive logic blocks.
Figure 3.2
Transmit and Receive Functions
3.2.1.1 MAC Transmit Function
The normal E-110 MAC architecture includes an independent transmit
function between the transmit logic on the host side and the MII, which
is located on the PHY side. The transmit logic block is customer-defined
and buffers data from the host. The E-110 MAC transmit function block
performs the E-110 MAC operations. Figure 3.3 shows how the transmit
function interfaces to the rest of the system.
Figure 3.3
Transmit Function Interface
Byte Stream
to Host
Transmit
Function
Receive
Function
Transmit
Nibbles
to MII
Receive
Nibbles
from MII
Transmit
Byte Stream
from Host
Receive
E-110 MAC Core
Transmit
Logic
Receive
Logic
Transmit
Logic
Transmit
Function
External MII PHY
Transmit
Byte Stream
MAC
E-110
Control
Status
Transmit Statistics
Host
Statistics
Logic
MII
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