參數(shù)資料
型號(hào): E-110
廠商: LSI Corporation
英文描述: 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core)
中文描述: 100兆- T的快速以太網(wǎng)核心(100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心)
文件頁數(shù): 97/130頁
文件大?。?/td> 770K
代理商: E-110
4-1
Chapter 4
Functional Timing
This chapter examines various E-110 functional timing scenarios. The
key timing relationships are discussed. For details of the operation of
each of the signals discussed, refer to Chapter 2, “Signal Descriptions.”
This chapter contains the following sections:
Section 4.1, “MAC Functional Timing”
Section 4.2, “MIIM Core Functional Timing”
Section 4.3, “Transmit Collision Functional Timing”
4.1 MAC Functional Timing
The following subsections describe the functional timing for MAC
operations, including MAC receive and transmit packet timing.
4.1.1 MAC Receive Packet Timing
The timing for a typical receive packet is shown in Figure 4.1. Notice that
the PHY asserts the MCRS and MRXDV signals at the beginning of
packet reception. The PHY asserts MCRS asynchronously as soon as it
detects a non-idle medium. The PHY also asserts MRXDV
synchronously to the rising edge of MRXC when it has decoded a valid
preamble.
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