參數(shù)資料
型號: E-110
廠商: LSI Corporation
英文描述: 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core)
中文描述: 100兆- T的快速以太網(wǎng)核心(100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心)
文件頁數(shù): 60/130頁
文件大?。?/td> 770K
代理商: E-110
2-28
Signal Descriptions
scan data can be shifted in on the TEST_SI pin. TEST_SE
must be kept deasserted during normal operation.
TEST_SI
Scan Input
The TEST_SI signal is the serial scan chain input pin.
When the TMODE and TEST_SE signals are asserted,
test data can be presented to the MAC on the TEST_SI
pin.
Input
TEST_SO
Scan Output
The TEST_SO signal is the serial scan chain output pin.
The data presented on TEST_SO is the output data that
results from the input stimulus on TEST_SI.
Output
2.2 MAC Control Module Signals
The interface diagram for the optional MAC control module core is shown
in Figure 2.2. The signals fall into the following groups:
E-110 MAC core signals
PHY
Host Signals
Figure 2.2
MAC Control Module Core Interface Diagram
RPSF
RPEF
RPDV
MRXC
TPDN
RRST_L
TRST_L
TPSF
RPD[7:0]
E-110
MAC
Core
RSV_GOOD
TPAB
MAC
Control
Module
Core
FLOWCON_EN
PAUSE_MIRROR[23:0]
CTLP
PAUSE_ACTIVE
HST_TPSF
RCV_LOAD_DLY[3:0]
UNSUPP_OPCODE
PAUSE_TIME_IN[15:0]
RSVD_PAUSEF
PAUSE_RSVP_L
RCVNG_PAUSE_FRAME
ADDR_MATCH
XMT_PAUSEF
Signals
Host
Signals
MTXC
PHY
Signals
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