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參數(shù)資料
| 型號： | E-110 |
| 廠商： | LSI Corporation |
| 英文描述： | 100BASE-T Fast Ethernet Core(100BASE-T快速以太網(wǎng)處理芯片 Fast Ethernet Core) |
| 中文描述： | 100兆- T的快速以太網(wǎng)核心（100兆- T的快速以太網(wǎng)處理芯片快速以太網(wǎng)核心） |
| 文件頁數(shù)： | 44/130頁 |
| 文件大?。?/td> | 770K |
| 代理商： | E-110 |
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2-12
Signal Descriptions
the PHY can keep MRXC in either the HIGH or LOW con-
dition to extend the MRXC clock by one cycle until the
PHY is ready to provide MRXC from a nominal clock
source. The maximum HIGH or LOW time for MRXC dur-
ing this transition is two times the nominal clock period (a
total of 80 ns for 25-MHz operation or 800 ns for 2.5-MHz
operation).
MRXD[3:0]
Receive Nibble Data
MRXD[3:0] [RXD] consists of four data signals that the
PHY drives synchronously to the rising edge of the
MRXC clock. For each MRXC period in which MRXDV is
asserted, the PHY transfers four bits of data over the
MRXD[3:0] signals to the E-110 MAC. MRXD[0] is the
least significant bit. When MRXDV is deasserted, the
MRXD[3:0] signals have no effect on the E-110 MAC.
Input
For a frame to be correctly interpreted by the E-110 MAC,
a completely formed SFD must be passed across the
interface. A completely formed SFD is the octet
0b1010.1011, which follows seven identical octets of pre-
amble (0b1010.1010).
MRXDV
Receive Data Valid
The PHY asserts the MRXDV [RX_DV] signal to indicate
that the PHY is presenting recovered and decoded nib-
bles on the MRXD[3:0] [RXD[3:0]] signals and that MRXC
is synchronous to the recovered data. The PHY asserts
MRXDV synchronously to the rising edge of MRXC. The
PHY keeps MRXDV asserted from the first recovered nib-
ble of the frame through the final recovered nibble and
deasserts it prior to the first MRXC that follows the final
nibble. MRXDV encompasses the frame, starting no later
than the SFD and excluding any end of frame delimiter
The PHY may also assert MRXDV for transferring a
validly decoded preamble.
Input
MRXER
Receive Error
The PHY asserts the MRXER [RX_ER] signal to indicate
to the E-110 MAC that a media error (for example, a
coding error) was detected somewhere in the frame pres-
ently being transferred from the PHY to the E-110 MAC.
The PHY asserts MRXER synchronously to the rising
edge of MRXC for one or more MRXC periods and then
Input
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