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| 型號(hào)： | MCF5249VM140 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 140 MHz, RISC PROCESSOR, PBGA160 |
| 封裝： | 15 X 15 MM, MAPBGA-160 |
| 文件頁(yè)數(shù)： | 143/454頁(yè) |
| 文件大?。?/td> | 6701K |
| 代理商： | MCF5249VM140 |
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DMA Transfer Functional Description
MOTOROLA
DMA Controller Module
14-17
Note: If the auto-align bit (AA = DCR[28]) is set, error checking is performed on the
appropriate registers only.
A read/write transfer refers to a dual-address access in which a number of bytes are read from the source
address and written to the destination address. The number of bytes in the transfer is determined by the
larger of the sizes specified by the source and destination size encoding. See Table 14-20 and Table
The source and destination address registers (SAR and DAR) increment at the completion of a successful
address phase. The BCR decrements at the completion of a successful address write phase. A successful
address phase occurs when a valid address request is not held by the arbiter.
14.7.1
CHANNEL INITIALIZATION AND STARTUP
Before starting a block transfer operation, the channel registers must be initialized with information
describing the channel configuration, request-generation method, and data block. This initialization is
accomplished by programming the appropriate information into the channel registers.
14.7.1.1
Channel Prioritization
The four DMA channels are prioritized in ascending order (channel 0 having highest priority and channel 3
having the lowest) or as determined by the BWC bits in the DCR. If the BWC bits for a DMA channel are
set to 000, then that channel has priority over the channel immediately preceding it. For example, if DMA
channel 3 has the BWC bits set to 000, it has priority over DMA channel 2 but not over DMA channel 1.
This is assuming that DMA channel 2 has something other than all zeroes in the BWC bits.
Another example would be the case where the BWC bits in only DMA 2 and DMA 1 are all zeroes. In this
case, DMA 1 would have priority over DMA 0 and DMA 2. The BWC bits being zero in DMA 2 in this case
have no effect on prioritization.
In the case of simultaneous external requests, the prioritization is either ascending or as determined by
each channels BWC bits as described in the previous paragraphs.
14.7.1.2
Programming the DMA
The following are some general comments on programming the DMA:
No mechanism exists for preventing writes to control registers during DMA accesses
If the BWC of sequential channels are equivalent, channel priority is in ascending order
The SAR is loaded with the source (read) address. If the transfer is from a peripheral device to memory,
the source address is the location of the peripheral data register. If the transfer is from memory to a
peripheral device or memory to memory, the source address is the starting address of the data block. This
address can be any byte address.
The DAR should contain the destination (write) address. If the transfer is from a peripheral device to
memory, or memory to memory, the DAR is loaded with the starting address of the data block to be written.
If the transfer is from memory to a peripheral device, the DAR is loaded with the address of the peripheral
data register. This address can be any byte address.
The manner in which the SAR and DAR change after each cycle depends on the values in the DCR SSIZE
and DSIZE fields and the SINC and DINC bits, and the starting address in the SAR and DAR. If
programmed to increment, the increment value is 1, 2, 4, or 16 for byte, word, longword, or line operands,
respectively. If the address register is programmed to remain unchanged (no count), the register is not
incremented after the operand transfer.
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| MCF5249VF140 | 32-BIT, 140 MHz, RISC PROCESSOR, PBGA160 |
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