9-20
MCF5249UM
MOTOROLA
CPU STOP Instruction
9.5.2.3
Software Watchdog Service Register
The SWSR is where the SWT servicing sequence should be written. To prevent an SWT timeout, users
should write a $55 followed by a $AA to this register. Both writes must be performed in the order listed prior
to the SWT timeout, but any number of instructions or accesses to the SWSR can be executed between
the two writes. If the SWT has already timed out, writing to this register will have no effect in negating the
SWT interrupt. The following register illustrates the SWSR programming model.
The SWSR is an 8-bit write-only register. At system reset, the contents of SWSR are uninitialized.
9.6
CPU STOP INSTRUCTION
Executing the CPU STOP instruction does not stop any of the clocks.
9.7
MCF5249 BUS ARBITRATION CONTROL
9.7.1
DEFAULT BUS MASTER PARK REGISTER
The MPARK determines the default bus master arbitration between internal transfers. This arbitration is
needed because there are two bus masters inside the MCF5249. One is the CPU, the other is the DMA
unit. Both can access internal registers within the MCF5249 peripherals.
Table 9-33 shows the MPARK
register bit encoding.
The MPARK is an 8-bit read-write register.
9.7.1.1
Internal Arbitration Operation
The PARK[1:0] bits are programmed to indicate the priority of internal transfers within MCF5249
resources. The possible masters that can initiate internal transfers internal to the MCF5249 are the core
and the on-chip DMAs. Since the priority between DMAs is resolved by their relative priority amongst each
other and by programming the BWC bits in their respective DMA control registers (see
14.4.5 DMA ControlRegister), the MPARK bits need only arbitrate priority between the core and the DMA module (which
contains all four DMA channels) for internally generated transfers.
Table 9-32 Software Watchdog Service Register (SWSR)
BITS
7
6
5
4
3
2
1
0
FIELD
SWSR7
SWSR6
SWSR5
SWSR4
SWSR3
SWSR2
SWSR1
SWSR0
RESET
----
---
-
R/W
ADDR
MBAR + $(0X03)
Table 9-33 Default Bus Master Register (MPARK)
BITS
7
6
5
4
3
2
1
0
FIELD
PARK[1]
PARK[0]
IARBCTRL
EARBCTRL
SHOWDATA
-
BCR24BIT
RESET
0
R/W
ADDR
MBAR + $(0X0C)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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