Processor Interface Overview
MOTOROLA
Audio Functions
17-31
The implementation of all data out FIFOs is a double FIFO, one for left and one for right. The Empty
exception is set when both FIFOs are empty. The Underrun/Overrun exception is set when one of the
FIFOs is underrun or is overrun. Resync is set when the hardware resynchronizes left and right FIFOs.
On receiving an Underrun/Overrun interrupt, synchronization between Left and Right words in the FIFOs
may be lost. Synchronization will not be lost when the underrun or overrun comes from the audio side of
the FIFO. If the processor reads or writes more data from, for example, the left than from the right,
synchronization will be lost. If automatic resynchronization is enabled, and if the software obeys the rules
to let this work, resynchronization will be automatic.
Table 17-31 Interrupt Register Description (0x94, 0x98)
BIT
INTERRUPT NAME
DESCRIPTION
HOW TO CLEAR
31
iis1TxUnOv
iis1 transmit fifo under/overrun
reg. IntClear
30
iis1TxResyn
iis1 transmit fifo resync
reg. IntClear
29
iis2TxUnOv
iis2 transmit fifo under/overrun
reg. IntClear
28
iis2TxResyn
iis2 transmit fifo underrun
reg. IntClear
27
ebuTxUnOv
IEC958 transmit fifo under/overrun
reg. IntClear
26
ebuTxResyn
IEC958 transmit fifo resync
reg. IntClear
25
ebuCNew
IEC958 receiver change in value of
Control channel
reg. IntClear
24
Iec958ValNoGood
IEC958 validity flag no good
reg. IntClear
23
ebuSymErr
IEC958 receiver found illegal symbol
reg. IntClear
22
ebuBitErr
IEC958 receiver found parity bit error
reg. IntClear
21
UChanTxEm
UChannelTransmit register empty
write to tx reg
20
UChanTxUnder
UchannelTransmit register underrun
reg. IntClear
19
UChanTx-NextFirst
UchannelTransmit register next byte will
be first
write to Tx reg
18
UChanRcvFull
UChannelReceive register full
read Rcv reg
17
UChanRcvOver
UChannelReceive register overrun
reg. IntClear
16
QChanRvFull
QChannelReceive register full
read rcv reg
15
QChanOverrun
QChannelReceive register overrun
reg. IntClear
14
UQChanSync
U/Q channel sync found
reg. IntClear
13
UQChanErr
U/Q channel framing error
reg IntClear
12
Pdir1UnOv
Processor data input underrun/overrun
reg IntClear
11
Pdir1Resyn
Processor data input resync
reg IntClear
10
Pdir2UnOv
Processor data input underrun/overrun
reg IntClear
9
Pdir2Resyn
Processor data input resync
reg IntClear
8
audioTick
audio tick interrupt
reg IntClear
7
6
5
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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