
Supply Voltage Sequencing and Separation Cautions
MOTOROLA
Electrical Specifications
21-3
21.1
SUPPLY VOLTAGE SEQUENCING AND SEPARATION
CAUTIONS
Figure 21-1 shows two situations to avoid in sequencing the CoreVdd and PADVdd (I/O) and PLL
supplies.
Figure 21-1 Supply Voltage Sequencing and Separation Cautions
CoreVdd supply should not be allowed to rise early (1). This is usually avoided by running the regulator for
the CoreVdd supply (1.8 V) from the voltage generated by the 3.3V supply (PADVdd) (See Figure 5-2).
This keeps the CoreVdd supply from rising faster than PADVdd supply.
Also CoreVdd, PLLGVdd, PLLCVdd supply should not rise so late that a large voltage difference is allowed
between the two supplies (2). Typically this situation is avoided by using external discrete diodes in series
between supplies as shown in
Figure 21-2. The series diodes forward bias when the difference between
PADVdd and CoreVdd reaches approximately 2.1V, causing CoreVdd to rise as PADVdd ramps up. When
the CoreVdd regulator begins proper operation, the difference between supplies should not exceed 1.5 V
and conduction through the diode chain reduces to essentially leakage current.
During supply sequencing, the following general relationship should be adhered to: PADVdd, >= CoreVdd,
PLLGVdd, >= (PADVdd - 2.1 V).
The PLL core supplies (PLLGVdd and PLLCVdd) should comply with these constraints just as the
CoreVdd does. In practice, PLLGVdd and PLLCVdd are typically connected directly to the CoreVdd with
some filtering. Further, the PLL PAD supply (PLL1VDD) would be connected directly to the PAD supply via
some filtering.
PADVdd, (PLL1Vdd)
CoreVdd, (PLLGVdd, PLLCVdd)
Time
3.3V
1.8V
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Notes:
1ICoreVdd, PLLGVdd, PLLCVddVcc, PVcc rising before PADVdd, PLL1Vdd
2PADVdd, PLL1Vdd rising much faster than CoreVdd, PLLGVdd, PLLCVdd
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Supplies Stable
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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