
3-10
MCF5249UM
MOTOROLA
Processor Exceptions
3.5
PROCESSOR EXCEPTIONS
3.5.1
ACCESS ERROR EXCEPTION
The exact processor response to an access error depends on the type of memory reference being
performed. For an instruction fetch, the processor postpones the error reporting until the faulted reference
is needed by an instruction for execution. Therefore, faults that occur during instruction prefetches that are
then followed by a change of instruction flow do not generate an exception. When the processor attempts
to execute an instruction with a faulted opword and/or extension words, the access error is signaled and
the instruction aborted. For this type of exception, the programming model has not been altered by the
instruction generating the access error.
If the access error occurs on an operand read, the processor immediately aborts the current instruction’s
execution and initiates exception processing. In this situation, any address register updates attributable to
the auto-addressing modes, (e.g., (An)+,-(An)), have already been performed, so the programming model
contains the updated An value. In addition, if an access error occurs during the execution of a MOVEM
instruction loading from memory, any registers already updated before the fault occurs contains the
operands from memory.
The ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes.
Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the
signaling of an access error appears to be decoupled from the instruction that generated the write.
Accordingly, the PC contained in the exception stack frame merely represents the location in the program
when the access error was signaled. All programming model updates associated with the write instruction
are completed. The NOP instruction can collect access errors for writes. This instruction delays its
execution until all previous operations, including all pending write operations, are complete. If any previous
write terminates with an access error, it is guaranteed to be reported on the NOP instruction.
3.5.2
ADDRESS ERROR EXCEPTION
Any attempted execution transferring control to an odd instruction address (i.e., if bit 0 of the target
address is set) results in an address error exception.
Any attempted use of a word-sized index register (Xn.w) or a scale factor of 8 on an indexed effective
addressing mode generates an address error as does an attempted execution of a full-format indexed
addressing mode.
3.5.3
ILLEGAL INSTRUCTION EXCEPTION
The MCF5249 processors decode the full 16-bit opcode and generate this exception if execution of an
unsupported instruction is attempted. Additionally, attempting to execute an illegal line A or line F opcode
generates unique exception types: vectors 10 and 11, respectively.
ColdFire processors do not provide illegal instruction detection on extension words of any instruction,
including MOVEC. Attempting to execute an instruction with an illegal extension word causes undefined
results.
3.5.4
DIVIDE BY ZERO
Attempted division by zero causes an exception (vector 5, offset = 0x014) except when the PC points to
the faulting instruction (DIVU, DIVS, REMU, REMS).
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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