參數(shù)資料
型號(hào)： TSB12LV01BPZ
英文描述： FPGA (Field-Programmable Gate Array)
中文描述： 總線控制器
文件頁(yè)數(shù)： 14/106頁(yè)
文件大?。?/td> 605K
代理商： TSB12LV01BPZ
1
–
6
Table 1
–
1. Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
Data-Mover Port Interface
DMD0
–
DMD15
26
–
29
31
–
34
36
–
39
41
–
44
I/O
Data mover (DM) bidirectional data port. DMD0 is the MSB of these 16 bits.
DMCLK
46
O
Data mover clock at (SCLK/2) MHz
DMDONE
50
O
Data mover done. For transmit, this will be activated when the packet per block
counter in the CFR counts down to zero. For receive, this terminal will pulse for
one DMCLK prior to the first byte/word available to the DM interface.
DMERROR
52
O
Data mover error. DMERROR is asserted high when there is an error in the
received packet or an illegal transmit speed was attempted.
DMPRE
48
O
Data mover predata indicator. In transmit mode, DMPRE pulses for one DMCLK
prior to sending the first quadlet. In isochronous receive mode, DMPRE will pulse
for one DMCLK when the sync bit in the header matches a bit set in the
isochronous register. DMPRE is not used in asynchronous receive mode.
DMREADY
77
I
Data mover ready. Must be asserted high by the external logic controlling the DM
interface when it is ready to supply data for transmit. DMREADY must be set low
when the data mover is in receive mode.
DMRW
49
O
Data mover read/write indicator. When data is being moved from 1394 to the DM
port (receive) this signal will go active high to indicate data is available on
DMD[0:15]. When data is being moved from DM to 1394 bus (transmit) this signal
will go active high to indicate that data must be supplied to the DMD[0:15] port for
transmission.
PKTFLAG
51
O
Packet flag. When set, PKTFLAG is asserted high to indicate the first (header) or
last (trailer) quadlet of a received packet on the DM interface. PKTFLAG is not
valid in transmit mode.
Phy/Link Interface
CTL0, CTL1
70, 69
I/O
Phy-link interface control lines.
D0
–
D7
67, 66,
63
–
58
I/O
Phy-link interface data lines. Data is only expected on D0 and D1 at 100 Mbit/s,
D0
–
D3 at 200 Mbit/s, and D0
–
D7 at 400 Mbit/s. D0 is the MSB bit.
LINKON
64
I
Link-on from the Phy is a 4 MHz
–
8 MHz clock. This signal will be activated when
the link is inactive and the Phy has detected a link-on packet or a Phy interrupt.
This clock will persist for no more than 500 ns. When the link detects this terminal
as active, it will turn on and drive LPS.
LPS
53
O
Link power status. LPS is used to drive the LPS input to the Phy. It indicates to the
Phy that the link is powered up and active. LPS toggles at a rate = 1/16 of BCLK.
LREQ
74
O
Link request to Phy. LREQ makes bus requests and register access requests to
the Phy.
SCLK
72
I
System clock. SCLK is a 49.152 MHz clock supplied by the Phy. DMCLK is
generated from SCLK.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB12LV01BPZT 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01BPZTG4 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB12LV01PZ 制造商:Rochester Electronics LLC 功能描述:- Bulk
TSB12LV21 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER
TSB12LV21A 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE
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