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參數(shù)資料
| 型號： | TSB12LV01BPZ |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 51/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV01BPZ |
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3
–
14
BCLK
MWR
MCS
MCA
MA[0:6]
MD[0:15]
TEA
M8BIT/
SIZ0
MCMODE/
SIZ1
XX
XX
XX
XXXX
XXXX
XXXX
S0
S1
D0
S2
H0
H1
H2
S3
S4
H3
H4
D2
D1
S5
H5
ADDRESS
DATA
ADDRESS
DATA
3.3.5
The term
endianness
refers to the way data is referenced and stored in a processor
’
s memory. For example,
consider a 32-bit processor; any 32-word consists of four bytes which may be stored in memory in one of
two ways. Of the four bytes, either byte 3 will be considered the most significant byte and byte 0 the least
significant byte, or vice versa (see Figures 3
–
15 and 3
–
16). A little endian type memory considers byte 0
the least significant byte, whereas a big endian type memory considers byte 3 to be the least significant byte.
Endian Swapping
Byte #0
(Most Significant Byte)
Byte #1
Byte #2
Byte #3
(Least Significant Byte)
Figure 3
–
15. Big Endian Format
Byte #3
(Most Significant Byte)
Byte #2
Byte #1
Byte #0
(Least Significant Byte)
Figure 3
–
16. Little Endian Format
The TSB12LV32 configuration register space (CFR) and FIFO memory, both of which are 32-bits wide, use
a big endian architecture. The TSB12LV32 uses the same endianness as the internal P1394 link core. This
means that the most significant byte is the left-most byte (byte 0) and the least significant byte is the right
most byte (byte 3).
3.3.5.1
For little-endian processors, there are two modes of byte swapping, address invariant and data invariant.
Address invariance preserves byte ordering between the internal system (GP2Lynx registers and FIFO) and
external system (microcontroller/processor). Data invariance preserves the bit significance of the data, but
changes the byte significance between the internal and external systems. The MDINV pin controls how the
write/read data is swapped at the data bus (i.e., determines how the received bytes from the microcontroller
are mapped into the TSB12LV32 internal registers and memory space). Note that when the COLDFIRE pin
is high, the MDINV pin has no affect and data is always interpreted in as big endian. Refer to Literature
Data and Address Invariance for Little Endian Processors
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB12LV26-EP | 672-pin FineLine BGA |
| TSB12LV22PZP | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB12LV26PZ | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01PZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB12LV21 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER |
| TSB12LV21A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE |
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