參數(shù)資料
型號： TSB12LV01BPZ
英文描述： FPGA (Field-Programmable Gate Array)
中文描述： 總線控制器
文件頁數(shù)： 98/106頁
文件大?。?/td> 605K
代理商： TSB12LV01BPZ
8
–
5
To send an acknowledge packet, the TSB12LV32 must issue an immediate bus request (ImmReq) during
the reception of the packet addressed to it. This is required in order to minimize the idle gap between the
end of the received packet and the start of the transmitted acknowledge packet. As soon as the receive
packet ends, the Phy immediately grants control of the bus to the TSB12LV32. The TSB12LV32 sends an
acknowledgment to the sender unless the header CRC of the received packet is corrupted. In this case, the
TSB12LV32 does not transmit an acknowledge, but instead cancels the transmit operation and releases the
interface immediately; the TSB12LV32 must not use this grant to send another type of packet. After the
interface is released the TSB12LV32 may proceed with another request.
The TSB12LV32 may make only one bus request at a time. Once the TSB12LV32 issues any request for
bus access (ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another bus request until the Phy
indicates that the bus request was lost (bus arbitration lost and another packet received), or won (bus
arbitration won and the TSB12LV32 granted control). The Phy ignores new bus requests while a previous
bus request is pending. All bus requests are cleared upon a bus reset.
For write register requests, the Phy loads the specified data into the addressed register as soon as the
request transfer is complete. For read register requests, the Phy returns the contents of the addressed
register to the TSB12LV32 at the next opportunity through a status transfer. If a received packet interrupts
the status transfer, then the Phy continues to attempt the transfer of the requested register until it is
successful. A write or read register request may be made at any time, including while a bus request is
pending. Once a read register request is made, the Phy ignores further read register requests until the
register contents are successfully transferred to the TSB12LV32. A bus reset does not clear a pending read
register request.
The TSB41LV03A includes several arbitration acceleration enhancements, which allow the Phy to improve
bus performance and throughput by reducing the number and length of interpacket gaps. These
enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and
priority packet concatenation onto acknowledge packets, and accelerated fair and priority request
arbitration following acknowledge packets. The enhancements are enabled when the EAA bit in Phy register
5 is set.
The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit
the cycle start message under certain circumstances. The acceleration control request is therefore provided
to allow the TSB12LV32 to temporarily enable or disable the arbitration acceleration enhancements of the
TSB41LV03A during the asynchronous period. The TSB12LV32 typically disables the enhancements when
its internal cycle counter rolls over indicating that a cycle start message is imminent, and then re-enables
the enhancements when it receives a cycle start message. The acceleration control request may be made
at any time, however, and is immediately serviced by the Phy. Additionally, a bus reset or isochronous bus
request will cause the enhancements to be re-enabled, if the EAA bit is set.
8.3
Status Transfer
A status transfer is initiated by the Phy when there is status information to be transferred to the TSB12LV32.
The Phy waits until the interface is idle before starting the transfer. The transfer is initiated by the Phy
asserting status (
‘
b01) on the CTL terminals, along with the first two bits of status information on the D[0:1]
terminals. The Phy maintains CTL = status for the duration of the status transfer. The Phy may prematurely
end a status transfer by asserting something other than status on the CTL terminals. This occurs if a packet
is received before the status transfer completes. The Phy continues to attempt to complete the transfer until
all status information has been successfully transmitted. There is at least one idle cycle between
consecutive status transfers.
The Phy normally sends just the first four bits of status to the TSB12LV32. These bits are status flags that
are needed by the TSB12LV32 state machines. The Phy sends an entire 16-bit status packet to the
TSB12LV32 after a read register request, or when the Phy has pertinent information to send to the
TSB12LV32 or transaction layers. The only defined condition where the Phy automatically sends a register
to the TSB12LV32 is after self-ID, where the Phy sends the physical-ID register that contains the new node
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