參數(shù)資料
型號(hào)： TSB12LV01BPZ
英文描述： FPGA (Field-Programmable Gate Array)
中文描述： 總線控制器
文件頁(yè)數(shù)： 25/106頁(yè)
文件大小： 605K
代理商： TSB12LV01BPZ
2
–
9
2.2.4
Interrupt/Interrupt Mask Register at 0Ch and 10h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
A
29 30 31
28
P
S
S
R
P
S
C
C
C
C
C
I
A
S
H
I
A
P
C
D
R
A
T
M
D
F
L
The interrupt and interrupt mask register work in tandem to inform the host bus interface when the state of
the TSB12LV32 changes. The interrupt register is at 0Ch, the interrupt mask register is at 10h. The interrupt
register powers up all 0s, however, the interrupt mask register powers up with the INT and the MCERROR
bit set, i.e. 8000_1000h. The mask bits allows individual control for each interrupt. A 1 in the mask bit field
allows the corresponding interrupt in the interrupt register to be generated. Once an interrupt is generated
it must be cleared by writing a 1 to the bit in the interrupt register. For testing, each interrupt bit can be set
manually. This is done by first setting the REGRW bit at20h and then setting the individual interrupt bit. This
is also true for bit 0 at0Ch. In this test mode, the interrupt mask register is not used and has no effect.
BIT
NUMBER
BIT NAME
FUNCTION
DIR
DESCRIPTION
0
INT
Interrupt
R/W
INT contains the value of all interrupt and interrupt mask bits
ORed together
1
PHINT
Phy chip
interrupt
R/W
When PHINT is set, the Phy has signalled an interrupt
through the Phy interface
2
PHRRX
Phy register
information
received
R/W
When PHRRX is set, a register value has been transferred to
the Phy access register (offset 24h) from the Phy interface
3
PHRST
Phy reset
started
R/W
When PHRST is set, a Phy-LLC reconfiguration has started
(1394 bus reset)
4
SELFIDEND
Self-ID
validated
R/W
Self-ID end. This bit is set at the end of the self-ID reporting
process. When this bit is set, the contentF of the bus reset
CFR at34h is valid.
5
ATSTARTED
Asynchronous
transfer started
R/W
Asynchronous transfer started. Activated when the bus has
been granted and the first quadlet from the FIFO is about to
be popped from the ATF.
6
RXGRFPKT
GRF packet
received
R/W
Receive packet to GRF. This bit is set whenever a complete
packet has been confirmed into the GRF (asynchronous or
isochronous).
7
CMDRST
CSR register
reset request
R/W
If CMDRST is set, the receiver has been sent a quadlet write
request to the Reset_Start CSR register(target address is
FFFF_F000_000Ch)
8
DMERROR
Data Mover
error
R/W
DM error. This bit will be set whenever there is an error in the
DM stream. For transmit, if the DM port is configured for byte
access and the speed code in the DM control register or the
asynchronous header register is set for 400 Mbps then this
bit will be set. Under this condition DMEN will be reset to 0
preventing further transmit. For receive this bit will be set if
there is a header or data CRC error or if the DM port is config-
ured for byte access and the data is received at 400 Mbps.
9
RXDMPKT
Data Mover
packet receive
R/W
Receive packet to DM. This bit is set whenever a packet is
received to the DM port.
10
SELFIDER
Self-ID packet
error
R/W
Set if an error in the self-ID quadlet/packet has been de-
tected.
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