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| 型號： | TSB12LV01BPZ |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 91/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV01BPZ |
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7
–
13
7.4
Based on the settings of the RXSID and FULLSID bits in the control register @08h, the self-ID packets can
be either ignored or received into the GRF. Refer to Table 7
–
13.
Receive Self-ID Packet
Table 7
–
13. GRF Receive Self-ID Setup Using Control Register Bits (RXSID and FULLSID)
RXSID
(bit 1)
FULLSID
(bit 2)
OPERATION
0
X
Self-ID packets are not received by the link.
1
0
Only the data quadlet (first quadlet) of the self-ID packets are received into the GRF.
1
1
soth the data quadlet (first quadlet) and the logical inverse quadlet (second quadlet) of all
Self-ID packets are received into the GRF.
Figures 7
–
17 and 7
–
18 show the format of a received self-ID packet. For completeness, the figures assume
the cable Phy on the bus implements the maximum number of ports allowed by the P1394a specification.
Both figures show one received self-ID packet. The contents are described in Table 7
–
14.
3
2
1
0
7
6
5
4
11
10
9
8
15
14
13
12
19
18
20 21
31
30
29
28
27
26
25
24
23
22
0
0
numofQuadlets
0
0
spd
0
0
ackCode
Self-ID Data Quadlet #0
0
0
0
17
16
L
L
Logical Inverse of the Self-ID Quadlet #0
Self-ID Data Quadlet #1
Logical Inverse of the Self-ID Quadlet #1
Self-ID Data Quadlet #2
Logical Inverse of theSelf-ID Quadlet #2
Figure 7
–
17. Receive Self-ID Packet Format (RXSID=1, FULLSID=1)
Figure 7
–
18 shows the format of the received self-ID packet when the FULLSID is cleared. In this case, only
the first quadlet of each self-ID packet is received in the GRF.
3
2
1
0
7
6
5
4
11
10
9
8
15
14
13
12
19
18
20 21
31
30
29
28
27
26
25
24
23
22
0
0
0
0
1
1
Self-ID Data Quadlet #0
0
0
0
17
16
Self-ID Data Quadlet #1
Self-ID Data Quadlet #2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 7
–
18. Receive Self-ID Packet Format (RXSID=1, FULLSID=0)
Table 7
–
14. Receive Self-ID Function
FIELD NAME
DESCRIPTION
Self-ID Data Quadlet
First 32-bits of the first self-ID packet
Logical Inverse of the
Self-ID Quadlet
Second 32-bits of the first self-ID packet
ACK
When the ACK field is set (0001), the data in the Self-ID packet is correct. When ACK is
≠
0001,
the data in the self-ID packet is incorrect.
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| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01PZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB12LV21 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER |
| TSB12LV21A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE |
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