參數(shù)資料
型號(hào)： TSB12LV01BPZ
英文描述： FPGA (Field-Programmable Gate Array)
中文描述： 總線控制器
文件頁(yè)數(shù)： 41/106頁(yè)
文件大小： 605K
代理商： TSB12LV01BPZ
3
–
4
3.3
The micro interface can be configured to operate in one of the following modes: handshake, fixed-timing,
or ColdFire mode. Burst transfers are only supported in the latter two modes.
3.3.1
Microcontroller Handshake Mode
Byte handshake read and word handshake read are shown in Figure 3
–
3 and Figure 3
–
4, respectively.
Microcontroller Interface Read/Write Timing
The MCS, MCA handshake timing sequence for a read transaction can be summarized as follows:
1.
The host takes MCS low to signal the start of access. When the rising edge of BCLK samples
MCS low and MWR high, the MD[0:15] lines are enabled and driven with the read value. For an
8-bit data bus, MD[0:7] lines are not used.
2.
Following the next rising edge of BCLK, the TSB12LV32 takes MCA low to signal that the
requested operation is complete. This is ensured to take place after two BCLK cycles. MCA
remains low with the MD lines containing valid read data until the micro interface releases MCS
(high state)
3.
The host takes MCS high to signal the end of the process.
4.
The TSB12LV32 takes MCA high to acknowledge the end of the access. This 3-states the MD
lines.
Another read or write transaction can begin after the next rising edge of BCLK. Note that data size is
determined by the MCMODE/SIZ1 and M8BIT/SIZ0 signals. The ColdFire signal is only asserted high when
the micro interface is operating in ColdFire mode.
BCLK
COLDFIRE
M8BIT/SIZ0
MCMODE/SIZ1
MWR
MCS
MCA
MCADR[0:6]
MD[0:7]
MD[8:15]
A1
D1
D2
A2
Figure 3
–
3. Byte Handshake Read
Figure 3
–
4 shows a word handshake read transaction. In this case, all 16 bits of the MD lines are used. Note
that MD[0] contains the MSB and MD[15] contains the LSB. As in the byte read case, another read or write
transaction can begin after the next rising edge of BCLK.
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