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| 型號： | TSB12LV01BPZ |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 87/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV01BPZ |
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7
–
9
7.3
The format of the Phy configuration packet is shown in Figure 7-12 and is described in Table 7-8. The Phy
configuration packet transmit contains two quadlets, which are loaded into the ATF. The first quadlet is
written to address 50h. The second quadlet is written to address 58h. The 00E0h in the first quadlet (bits
16
–
31) tells the TSB12LV32 that this quadlet is the Phy configuration packet. The Eh is then replaced with
0h before the packet is transmitted to the Phy interface.
Phy Configuration
3
2
1
0
7
6
5
4
11
10
9
8
15
14
13
12
19
18
20 21
31
30
29
28
27
26
25
24
23
22
0
0
root_ID
T
R
gap_cnt
0
0
0
0
0
0
0
0
1
1
1
0
0
Logical inverse of first 16 bits of first quadlet
1
1
1
1
1
1
1
1
1
1
1
1
1
1
tcode =
’
E
’
0
0
0
17
16
1
1
Figure 7
–
11. Phy Configuration Packet Format
The Phy configuration packet can perform the following functions:
Set the gap count field of all nodes on the bus to a new value. The gap count, if set intelligently,
can optimize bus performance.
Force a particular node to be the bus root after the next bus reset.
It is not valid to transmit a Phy configuration packet with both the R bit and T bit set to zero. This would cause
the packet to be interpreted as an extended Phy packet.
Table 7
–
7. Phy Configuration Packet Functions
FIELD NAME
DESCRIPTION
00
The 00 field is the Phy configuration packet identifier.
root_ID
The root_ID field is the physical_ID of the node to have its force_root bit set (only meaningful when R
is set).
R
When R is set, the force-root bit of the node identified in root_ID is set and the force_root bit of all
other nodes are cleared. When R is cleared, root_ID is ignored.
T
When T is set, the PHY_CONFIGURATION.gap_count field of all the nodes is set to the value in the
gap_cnt field.
gap_cnt
The gap_cnt field contains the new value for PHY_CONFIGURATION.gap_count for all nodes. This
value goes into effect immediately upon receipt and remains valid after the next bus reset. After the
second reset, gap_cnt is set to 63h unless a new Phy configuration packet is received.
The format of a received Phy-configuration packet is shown in Figure 7
–
12 and is described in Table 7
–
8.
When PHY_PKT_ENA (bit 3 of the control register @08h) is set, all Phy packets will be received in the GRF.
One HDRERR interrupt will be generated for every Phy packet received.
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| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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| TSB12LV01PZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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