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| 型號(hào)： | TSB12LV01BPZ |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 99/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV01BPZ |
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8
–
6
address. All status transfers are either 4 or 16 bits unless interrupted by a received packet. The status flags
are considered to have been successfully transmitted to the TSB12LV32 immediately upon being sent, even
if a received packet subsequently interrupts the status transfer. Register contents are considered to have
been successfully transmitted only when all 8 bits of the register have been sent. A status transfer is retried
after being interrupted only if any status flags remain to be sent, or if a register transfer has not yet completed.
The definition of the bits in the status transfer are shown in Table 8
–
9 and the timing is shown in Figure 8
–
3.
Table 8
–
10. Status Bits
BIT(S)
NAME
DESCRIPTION
0
Arbitration Reset Gap
Indicates that the Phy has detected that the bus has been idle for an arbitration
reset gap time (as defined in IEEE Std 1394
–
1995). This bit is used by the
TSB12LV32 in the busy/retry state machine.
1
Subaction Gap
Indicates that the Phy has detected that the bus has been idle for a subaction gap
time (as defined in IEEE Std 1394
–
1995). This bit is used by the TSB12LV32 to
detect the completion of an isochronous cycle.
2
Bus Reset
Indicates that the Phy has entered the bus reset start state.
3
Interrupt
Indicates that a Phy interrupt event has occurred. An interrupt event may be a
configuration time-out, cable-power voltage falling too low, a state time-out, or a
port status change.
4
–
7
Address
This field holds the address of the Phy register whose contents are being
transferred to the TSB12LV32.
8
–
15
Data
This field holds the register contents.
00
00
(a)
01
(b)
00
00
S[14:15]
S[0:1]
D0, D1
CTL0, CTL1
SYSCLK
Figure 8
–
3. Status Transfer Timing
The sequence of events for a status transfer is as follows:
Status transfer initiated. The Phy indicates a status transfer by asserting status on the CTL lines
along with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle).
Normally (unless interrupted by a receive operation), a status transfer will be either 2 or 8 cycles
long. A 2-cycle (4-bit) transfer occurs when only status information is to be sent. An 8-cycle
(16-bit) transfer occurs when register data is to be sent in addition to any status information.
Status transfer terminated. The Phy normally terminates a status transfer by asserting idle on the
CTL lines. The Phy may also interrupt a status transfer at any cycle by asserting receive on the
CTL lines to begin a receive operation. The Phy shall assert at least one cycle of idle between
consecutive status transfers.
8.4
Whenever the Phy detects the data-prefix state on the serial bus, it initiates a receive operation by asserting
Receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The Phy indicates
the start of a packet by placing the speed code (encoded as shown in Table 8
–
11 on the D terminals, followed
by packet data. The Phy holds the CTL terminals in the receive state until the last symbol of the packet has
Receive Operation
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| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TSB12LV01BPZT | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01BPZTG4 | 功能描述:1394 接口集成電路 High Perf 1394 3.3V Link Layer RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV01PZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB12LV21 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 LINK LAYER CONTROLLER |
| TSB12LV21A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 BUS TO PCI BUS INTERFACE |
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